View LTC3577EUFF-1TRPBF_6935717.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc3577/ltc3577-1 1 3577fa typical application features applications description highly integrated 6-channel portable pmic the ltc ? 3577 is a highly integrated power management ic for single cell li-ion/polymer battery applications. it includes a powerpath manager with automatic load priori- tization, a battery charger, an ideal diode, input overvoltage protection and numerous other internal protection features. the ltc3577 is designed to accurately charge from current limited supplies such as usb by automatically reducing charge current such that the sum of the load current and the charge current does not exceed the programmed input current limit (100ma or 500ma modes). the ltc3577 reduces the battery voltage at elevated temperatures to improve safety and reliability. ef? cient high current charg- ing from supplies up to 38v is available using the on-chip bat-track controller. the ltc3577 also includes a push- button input to control the three synchronous step-down switching regulators and system reset. the onboard led backlight boost circuitry can drive up to 10 series leds and includes versatile digital dimming via i 2 c input. the i 2 c input also controls two 150ma ldos as well as other operating modes and status read back. the ltc3577 is available in a low pro? le 4mm 7mm 0.75mm 44-pin qfn package. led driver ef? ciency (10 leds) n full featured li-ion/polymer charger/powerpath? controller with instant-on operation n triple adjustable high ef? ciency step-down switching regulators (800ma, 500ma, 500ma i out ) n 6a battery drain current in hard reset n bat-track? control for external hv buck dc/dcs n i 2 c adjustable sw slew rates for emi reduction n high temperature battery voltage reduction improves safety and reliability n overvoltage protection for usb (v bus )/wall inputs provides protection to 30v n integrated 40v series led backlight driver with 60db brightness control and gradation via i 2 c n 1.5a maximum charge current with thermal limiting n battery float voltage: 4.2v (ltc3577) 4.1v (ltc3577-1) n pushbutton on/off control with system reset n dual 150ma current limited ldos n small 4mm 7mm 44-pin qfn package n pnds, dmb/dvb-h; digital/satellite radio; media players n portable industrial/medical products n universal remotes, photo viewers n other usb-based handheld products l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and powerpath and bat-track are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6522118, 6700364, 7511390, 5481178, 6580258. other patents pending. + 100ma/500ma 1000ma hv supply 8v to 38v (transients to 60v) usb charge pb 2 cc/cv charger led backlight with digitally controlled dimming dual ldo regulators ltc3577/ltc3577-1 triple high efficiency step-down switching regulators with pushbutton control high voltage buck dc/dc 0v single cell li-ion up to 10 led boost v out 0.8v to 3.6v/800ma 0.8v to 3.6v/150ma 0.8v to 3.6v/150ma 0.8v to 3.6v/500ma 0.8v to 3.6v/500ma ntc i 2 c port 3577 ta01a overvoltage protection optional led current (a) 20 efficiency (%) 30 50 60 80 90 1.e-06 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 3577 ta01b 10 70 40 0 max pwm constant current
ltc3577/ltc3577-1 2 3577fa table of contents features ...................................................................................................................... ...... 1 applications .................................................................................................................. ..... 1 typical application ........................................................................................................... .... 1 description.................................................................................................................... ..... 1 absolute maximum ratings ..................................................................................................... 3 order information ............................................................................................................. .... 3 pin con? guration ............................................................................................................. .... 3 electrical characteristics .................................................................................................... .... 4 typical performance characteristics .........................................................................................10 pin functions ................................................................................................................. ....16 block diagram ................................................................................................................. ...19 powerpath operation ........................................................................................................... ................................. 20 low dropout linear regulator operation ........................................................................................ ..................... 30 step-down switching regulator operation ....................................................................................... .................... 31 led backlight/boost operation ................................................................................................. ............................ 35 i 2 c operation ................................................................................................................... ..................................... 38 pushbutton interface operation ................................................................................................ ............................ 43 layout and thermal considerations ............................................................................................. ........................ 48 typical applications .......................................................................................................... ...50 package description ........................................................................................................... .52 related parts ................................................................................................................. ....53 revision history .............................................................................................................. ...54
ltc3577/ltc3577-1 3 3577fa pin configuration absolute maximum ratings v sw ............................................................ C0.3v to 45v v bus , v out , v in12 , v in3 , v inldo1 , v inldo2 , wall t < 1ms and duty cycle < 1% ................... C0.3v to 7v steady state ............................................ C0.3v to 6v chrg , bat, led_fs, led_ov, pwr_on, wake, pbstat, pg_dcdc, fb1, fb2, fb3, ldo1, ldo1_fb, ldo2, ldo2_fb, dv cc , scl, sda ............... C0.3v to 6v ntc, prog, clprog, on , i lim0 , i lim1 (note 4) ........................................... C0.3v to v cc + 0.3v i vbus , i vout , i bat , continuous (note 16) .....................2a i sw3 , continuous (note 16) ................................. 850ma i sw2 , i sw1 , continuous (note 16) ........................ 600ma i ldo1 , i ldo2 , continuous (note 16) ..................... 200ma i chrg , i acpr , i wake , i pbstat , i pg_dcdc ...................75ma i ovsens ..................................................................10ma i clprog , i prog , i led_fs , i led_ov ..............................2ma junction temperature ............................................110c operating temperature range ................. C40c to 85c storage temperature range .................. C65c to 125c (notes 1, 2, 3) top view 45 gnd uff package 44-lead (7mm s 4mm) plastic qfn i lim0 1 i lim1 2 led_fs 3 wall 4 sw3 5 v in3 6 fb3 7 ovsens 8 led_ov 9 dv cc 10 sda 11 scl 12 ovgate 13 pwr_on 14 on 15 37 idgate 36 prog 35 ntc 34 ntcbias 33 sw1 32 v in12 31 sw2 30 v inld02 29 ldo2 28 ldo1 27 ldo1_fb 26 fb1 25 fb2 24 ldo2_fb 23 v inldo1 pbstat 16 wake 17 sw 18 sw 19 sw 20 pg_dcdc 21 i led 22 44 chrg 43 clprog 42 v c 41 acpr 40 v bus 39 v out 38 bat t jmax = 110c, ja = 45c/w exposed pad (pin 45) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking package description temperature range ltc3577euff#pbf ltc3577euff#trpbf 3577 44-lead (4mm 7mm) plastic qfn C40c to 85c ltc3577euff-1#pbf ltc3577euff-1#trpbf 35771 44-lead (4mm 7mm) plastic qfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
ltc3577/ltc3577-1 4 3577fa electrical characteristics power manager . the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v bus = 5v, v bat = 3.8v, i lim0 = i lim1 = wall = 0v, v inldo1 = v inldo2 = v in12 = v in3 = v out , r prog = 2k, r clprog = 2.1k, unless otherwise noted. symbol parameter conditions min typ max units input power supply v bus input supply voltage 4.35 5.5 v i bus(lim) total input current (note 5) i lim0 = 0v, i lim1 = 0v (1x mode) i lim0 = 5v, i lim1 = 5v (5x mode) i lim0 = 5v, i lim1 = 0v (10x mode) l l l 80 450 900 90 475 950 100 500 1000 ma ma ma i busq input quiescent current, poff state 1x, 5x, 10x modes i lim0 = 0v, i lim1 = 5v (suspend mode) 0.42 0.042 0.1 ma ma h clprog ratio of measured v bus current to clprog program current 1000 ma/ma v clprog clprog servo voltage in current limit 1x mode 5x mode 10x mode 0.2 1.0 2.0 v v v v uvlo v bus undervoltage lockout rising threshold falling threshold 3.5 3.8 3.7 3.9 v v v duvlo v bus to v out differential undervoltage lockout rising threshold falling threshold 50 C50 100 mv mv r on_ilim input current limit power fet on- resistance (between v bus and v out ) 200 m battery charger v float v bat regulated output voltage ltc3577 ltc3577, 0 t a 85c ltc3577-1 ltc3577-1, 0 t a 85c 4.179 4.165 4.079 4.065 4.200 4.200 4.100 4.100 4.221 4.235 4.121 4.135 v v v v i chg constant-current mode charge current r prog = 1k, input current limit = 2a r prog = 2k, input current limit = 1a r prog = 5k, input current limit = 0.4a l l l 950 465 180 1000 500 200 1050 535 220 ma ma ma i batq_hr battery drain current, hard reset v bus = 0v, i out = 0a 7 15 a i batq_off battery drain current, poff state v bat = 4.3v, charger time out v bus = 0v 6 40 27 100 a a i batq_on battery drain current, pon state ldos, and led backlight disabled v bus = 0v, i out = 0a, no load on supplies, burst mode operation (note 10) 90 160 a v prog,chg prog pin servo voltage v bat > v trkl 1.000 v v prog,trkl prog pin servo voltage in trickle charge v bat < v trkl 0.100 v h prog ratio of i bat to prog pin current 1000 ma/ma i trkl trickle charge current v bat < v trkl 40 50 60 ma v trkl trickle charge rising threshold trickle charge falling threshold v bat rising v bat falling 2.5 2.85 2.75 3.0 v v v rechrg recharge battery threshold voltage threshold voltage relative to v float C75 C100 C125 mv t term safety timer termination period timer starts when v bat = v float C 50mv 3.2 4 4.8 hour t badbat bad battery termination time v bat < v trkl 0.4 0.5 0.6 hour h c/10 end-of-charge indication current ratio (note 6) 0.085 0.1 0.11 ma/ma r on_chg battery charger power fet on- resistance (between v out and bat) 200 m t lim junction temperature in constant temperature mode 110 c
ltc3577/ltc3577-1 5 3577fa electrical characteristics power manager . the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v bus = 5v, v bat = 3.8v, i lim0 = i lim1 = wall = 0v, v inldo1 = v inldo2 = v in12 = v in3 = v out , r prog = 2k, r clprog = 2.1k, unless otherwise noted. symbol parameter conditions min typ max units ntc, battery discharge protection v cold cold temperature fault threshold voltage rising ntc voltage hysteresis 75 76 1.3 77 %v ntcbias %v ntcbias v hot hot temperature fault threshold voltage falling ntc voltage hysteresis 34 35 1.3 36 %v ntcbias %v ntcbias v 2hot ntc discharge threshold voltage falling ntc voltage hysteresis 24.5 25.5 50 26.5 %v ntcbias mv i ntc ntc leakage current v ntc = v bus = 5v C50 50 na i bat2hot bat discharge current v bat = 4.1v, ntc < v too_hot 180 ma v bat2hot bat discharge threshold i bat < 0.1ma, ntc < v too_hot 3.9 v ideal diode v fwd forward voltage detection i out = 10ma 5 15 25 mv r dropout diode on-resistance, dropout i out = 200ma 200 m i max diode current limit (note 7) 3.6 a overvoltage protection v ovcutoff overvoltage protection threshold rising threshold, r ovsens = 6.2k 6.10 6.35 6.70 v v ovgate ovgate output voltage input below v ovcutoff input above v ovcutoff 1.88 ? v ovsens 12 0 v v i ovsensq ovsens quiescent current v ovsens = 5v 40 a t rise ovgate time to reach regulation c ovgate = 1nf 2.5 ms wall adapter v acpr acpr pin output high voltage acpr pin output low voltage i acpr = 0.1ma i acpr = 1ma v out C 0.3 v out 0 0.3 v v v w absolute wall input threshold voltage v wall rising v wall falling 3.1 4.3 3.2 4.45 v v v w differential wall input threshold voltage v wall C v bat falling v wall C v bat rising 025 75 100 mv mv i qwall wall operating quiescent current i wall + i vout , i bat = 0ma, wall = v out = 5v 440 a logic (i lim0 , i lim1 and chrg ) v il input low voltage i lim0 , i lim1 0.4 v v ih input high voltage i lim0 , i lim1 1.2 v i pd static pull-down current i lim0 , i lim1 ; v pin = 1v 2 a v chrg chrg pin output low voltage i chrg = 10ma 0.15 0.4 v i chrg chrg pin input current v bat = 4.5v, v chrg = 5v 0 1 a
ltc3577/ltc3577-1 6 3577fa electrical characteristics i 2 c interface. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. dv cc = 3.3v, v out = 3.8v, unless otherwise noted. symbol parameter conditions min typ max units dv cc input supply voltage 1.6 5.5 v i dvcc dv cc supply current scl = 400khz scl = sda = 0khz 1 0.4 a a v dvcc,uvlo dv cc uvlo 1.0 v v ih input high voltage 50 70 %dv cc v il input low voltage 30 50 %dv cc i ih input high leakage current sda = scl = dv cc = 5.5v C1 1 a i il input low leakage current sda = scl = 0v, dv cc = 5.5v C1 1 a v ol sda output low voltage i sda = 3ma 0.4 v timing characteristics (note 8) (all values are referenced to v ih and v il ) f scl scl clock frequency 400 khz t low low period of the scl clock 1.3 s t high high period of the scl clock 0.6 s t buf bus free time between stop and start condition 1.3 s t hd,sta hold time after (repeated) start condition 0.6 s t su,sta setup time for a repeated start condition 0.6 s t su,sto stop condition setup time 0.6 s t hd,dato output data hold time 0 900 ns t hd,dati input data hold time 0 ns t su,dat data setup time 100 ns t sp input spike suppression pulse width 50 ns step-down switching regulators. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v out = v in12 = v in3 = 3.8v, all regulators enabled unless otherwise noted. symbol parameter conditions min typ max units step-down switching regulators (buck1, buck2 and buck3) v in12 , v in3 input supply voltage (note 9) l 2.7 5.5 v v out uvlo v out falling v out rising v in12 and v in3 connected to v out through low impedance. switching regulators are disabled below v out uvlo 2.5 2.7 2.8 2.9 v v f osc oscillator frequency 1.91 2.25 2.59 mhz 800ma step-down switching regulator 3 (buck3 C pushbutton enabled, third in sequence) i vin3q pulse-skipping mode input current (note 10) 100 a burst mode operation input current (note 10) 17 a shutdown input current 0.01 a i lim3 peak pmos current limit (note 7) 1000 1400 1700 ma v fb3 feedback voltage pulse-skipping mode burst mode operation l l 0.78 0.78 0.8 0.8 0.82 0.824 v v i fb3 fb3 input current (note 10) C0.05 0.05 a d3 max duty cycle fb3 = 0v 100 % r p3 r ds(on) of pmos 0.3 r n3 r ds(on) of nmos 0.4
ltc3577/ltc3577-1 7 3577fa electrical characteristics step-down switching regulators. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v out = v in12 = v in3 = 3.8v, all regulators enabled unless otherwise noted. symbol parameter conditions min typ max units ldo regulator 1 (ldo1 C enabled via i 2 c) v inldo1 input voltage range v inldo1 v out + 0.3v l 1.65 5.5 v v out_uvlo v out falling v out rising ldo1 is disabled below v out uvlo 2.5 2.7 2.8 2.9 v v i qldo1_vo i qldo1_vi ld01 v out quiescent current ld01 v inldo1 quiescent current ldo1 enabled, pon state, i ldo1 = 0ma ldo1 enabled, pon state, i ldo1 = 0ma 18 0.1 30 2 a a i vinldo1 shutdown current ldo1 disabled, pon or poff state 0.01 1 a v ldo1_fb ldo1_fb regulated feedback voltage i ldo1 = 1ma l 0.78 0.8 0.82 v ldo1_fb line regulation (note 11) i ldo1 = 1ma, v in = 1.65v to 5.5v 0.4 mv/v ldo1_fb load regulation (note 11) i ldo1 = 1ma to 150ma 5 v/ma i ldo1_fb ldo1_fb input current ldo1_fb = 0.8v C50 50 na i ldo1_oc available output current l 150 ma symbol parameter conditions min typ max units r sw3_pd sw3 pull-down in shutdown poff state 10 k 500ma step-down switching regulator 2 (buck2 C pushbutton enabled, second in sequence) i vin12q pulse-skipping mode input current (note 10) 100 a burst mode operation input current (note 10) 17 a shutdown input current 0.01 a i lim2 peak pmos current limit (note 7) 650 900 1200 ma v fb2 feedback voltage pulse-skipping mode burst mode operation l l 0.78 0.78 0.8 0.8 0.82 0.824 v v i fb2 fb2 input current (note 10) C0.05 0.05 a d2 max duty cycle fb2 = 0v 100 % r p2 r ds(on) of pmos i sw2 = 100ma 0.6 r n2 r ds(on) of nmos i sw2 = C100ma 0.6 r sw2_pd sw2 pull-down in shutdown poff state 10 k 500ma step-down switching regulator 1 (buck1 C pushbutton enabled, first in sequence) i vin12q pulse-skipping mode input current (note 10) 100 a burst mode operation input current (note 10) 17 a shutdown input current 0.01 a i lim1 peak pmos current limit (note 7) 650 900 1200 ma v fb1 feedback voltage pulse-skipping mode burst mode operation l l 0.78 0.78 0.8 0.8 0.82 0.824 v v i fb1 fb1 input current (note 10) C0.05 0.05 a d1 max duty cycle fb1 = 0v 100 % r p1 r ds(on) of pmos i sw1 = 100ma 0.6 r n1 r ds(on) of nmos i sw1 = C100ma 0.6 r sw1_pd sw1 pull-down in shutdown poff state 10 k ldo regulators. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v inldo1 = v inldo2 = v out = v bat = 3.8v, ldo1 and ldo2 enabled unless otherwise noted.
ltc3577/ltc3577-1 8 3577fa electrical characteristics ldo regulators. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v inldo1 = v inldo2 = v out = v bat = 3.8v, ldo1 and ldo2 enabled unless otherwise noted. led boost switching regulator. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in3 = v out = 3.8v, r ov = 10m, r led_fs = 20k, boost regulator disabled unless otherwise noted. symbol parameter conditions min typ max units v in3 , v out operating supply range (note 9) l 2.7 5.5 v i vout_led operating quiescent current shutdown quiescent current (notes 10, 14) 560 0.01 a a v led_ov led_ov overvoltage threshold led_ov rising led_ov falling 0.6 1.0 0.85 1.25 v v i lim peak nmos switch current 800 1000 1200 ma i led_fs i led pin full-scale operating current 18 20 22 ma i led_dim i led pin full-scale dimming range 64 steps 60 db r nswon r ds(on) of nmos switch 240 m i nswoff nmos switch-off leakage current v sw = 5.5v 0.01 1 a f osc oscillator frequency 0.95 1.125 1.3 mhz v led_fs led_fs pin voltage l 780 800 820 mv i led_ov led_ov pin current r led_fs = 20k l 3.8 4 4.2 a d boost maximum duty cycle i led = 0 97 % v boostfb boost mode i led feedback voltage l 775 800 825 mv symbol parameter conditions min typ max units i ldo1_sc short-circuit output current 270 ma v drop1 dropout voltage (note 12) i ldo1 = 150ma, v inldo1 = 3.6v i ldo1 = 150ma, v inldo1 = 2.5v i ldo1 = 75ma, v inldo1 = 1.8v 160 200 170 260 320 280 mv mv mv r ldo1_pd output pull-down resistance in shutdown ldo1 disabled 10 k ldo regulator 2 (ldo2 C enabled via i 2 c) v inldo2 input voltage range v inldo2 v out + 0.3v l 1.65 5.5 v v out_uvlo v out falling v out rising ldo2 is disabled below v out uvlo 2.5 2.7 2.8 2.9 v v i qldo2_vo i qldo2_vi ldo2 v out quiescent current ldo2 v inldo2 quiescent current ldo2 enabled, pon state, i ldo2 = 0ma ldo2 enabled, pon state, i ldo2 = 0ma 18 0.1 30 2 a a i vinldo2 shutdown current ldo2 disabled, pon or poff state 0.01 1 a v ldo2_fb ldo2_fb regulated output voltage i ldo2 = 1ma l 0.78 0.8 0.82 v ldo2_fb line regulation (note 11) i ldo2 = 1ma, v in = 1.65v to 5.5v 0.4 mv/v ldo2_fb load regulation (note 11) i ldo2 = 1ma to 150ma 5 v/ma i ldo2_fb ldo2_fb input current ldo2_fb = 0.8v C50 50 na i ldo2_oc available output current l 150 ma i ldo2_sc short-circuit output current 270 ma v drop2 dropout voltage (note 12) i ldo2 = 150ma, v inldo2 = 3.6v i ldo2 = 150ma, v inldo2 = 2.5v i ldo1 = 75ma, v inldo1 = 1.8v 160 200 170 260 320 280 mv mv mv r ldo2_pd output pull-down resistance in shutdown ldo2 disabled 14 k
ltc3577/ltc3577-1 9 3577fa electrical characteristics pushbutton controller. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v out = 3.8v, unless otherwise noted. symbol parameter conditions min typ max units pushbutton pin ( on ) v out pushbutton operating supply range (note 9) l 2.7 5.5 v v out uvlo v out falling v out rising pushbutton is disabled below v out uvlo 2.5 2.7 2.8 2.9 v v v on _th on threshold rising on threshold falling 0.4 0.8 0.7 1.2 v v i on on input current v on = v out v on = 0v C1 C4 C9 1 C14 a a power-on input pin (pwr_on) v pwr_on pwr_on threshold rising pwr_on threshold falling 0.4 0.8 0.7 1.2 v v i pwr_on pwr_on input current v pwr_on = 3v C1 1 a status output pins (pbstat, wake, pg_dcdc) i pbstat pbstat output high leakage current v pbstat = 3v C1 1 a v pbstat pbstat output low voltage i pbstat = 3ma 0.1 0.4 v i wake wake output high leakage current v wake = 3v C1 1 a v wake wake low output voltage i wake = 3ma 0.1 0.4 v i pg_dcdc pg_dcdc output high leakage current v pg_dcdc = 3v C1 1 a v pg_dcdc pg_dcdc output low voltage i pg_dcdc = 3ma 0.1 0.4 v v thpg_dcdc pg_dcdc threshold voltage (note 13) C8 % pushbutton timing parameters t on_pbstat1 on low time to pbstat low wake high 50 ms t on_pbstat2 on high to pbstat high pbstat low > t pbstat_pw 900 s t on_wake on low time to wake high wake low > t pwr_onbk2 400 ms t on_hr on low to hard reset hard reset = all supplies disabled 4.2 5 5.8 seconds t pbstat_pw pbstat minimum pulse width 40 50 60 ms t wake_extp wake high from usb or wall present wake low > t pwr_onbk2 100 ms t wake_dcdc wake high to buck1 enable wake low > t pwr_onbk2 5s t pwr_onh pwr_on high to wake high wake low > t pwr_onbk2 50 ms t pwr_onl pwr_on low to wake low wake high > t pwr_onbk1 50 ms t pwr_onbk1 pwr_on power-up blanking wake r ising until pwr_on low recognized 5 seconds t pwr_onbk2 pwr_on power-down blanking wake falling until pwr_on high recognized 1 seconds t pg_dcdch bucks in regulation to pg_dcdc high all bucks within pg_dcdc threshold voltage 230 ms t pg_dcdcl bucks disabled to pg_dcdc low all bucks disabled 44 s
ltc3577/ltc3577-1 10 3577fa typical performance characteristics input supply current vs temperature input supply current vs temperature (suspend mode) battery drain current vs temperature electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3577e/ltc3577e-1 are guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: this ic includes over temperature protection that is intended to protect the device during momentary overload conditions. junction temperatures will exceed 110c when over temperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may result in device degradation or failure. note 4: v cc is the greater of v bus , v out or bat. note 5: total input current is the sum of quiescent current, i busq , and measured current given by v clprog /r clprog ? (h clprog + 1). note 6: h c/10 is expressed as a fraction of measured full charge current with indicated prog resistor. note 7: the current limit features of this part are intended to protect the ic from short term or intermittent fault conditions. continuous operation above the speci? ed maximum pin current rating may result in device degradation or failure. note 8: the serial port is tested at rated operating frequency. timing parameters are tested and/or guaranteed by design. note 9: v out not in uvlo. note 10: fb high, not switching. note 11: measured with the ldo running unity gain with output tied to feedback pin. note 12: dropout voltage is the minimum input to output voltage differential needed for an ldo to maintain regulation at a speci? ed output current. when an ldo is in dropout, its output voltage will be equal to v in C v drop . note 13: pg_dcdc threshold is expressed as a percentage difference from the buck1-3 regulation voltages. the threshold is measured from buck1-3 output rising. note 14: i vout_led is the sum of v out and v in3 current due to led driver. note 15: the i batq speci? cations represent the total battery load assuming v inldo1 , v inldo2 , v in12 and v in3 are tied directly to v out . note 16: long-term current density rating for the part. t a = 25c unless otherwise speci? ed temperature (c) C50 i vbus (ma) 0.7 25 3577 g01 0.4 0.2 C25 0 50 0.1 0 0.8 0.6 0.5 0.3 75 100 125 v bus = 5v 1x mode temperature (c) C50 C25 0 i vbus (ma) 0.04 0.10 0 50 75 3577 g02 0.02 0.08 0.06 25 100 125 v bus = 5v temperature (c) C50 0 i bat (a) 50 150 200 250 400 350 0 50 75 3577 g03 100 300 C25 25 100 125 pon state burst mode operation no load on supplies, ldos and led boost disabled. v bat = 3.8v, v bus = 0v poff state pon state pulse-skipping mode hard reset state
ltc3577/ltc3577-1 11 3577fa input current limit vs temperature input r on vs temperature charge current vs temperature (thermal regulation) temperature (c) C50 i vbus (ma) 400 1000 1100 1200 0 50 75 3577 g04 200 100 800 600 300 900 0 700 500 C25 25 100 125 v bus = 5v r clprog = 2.1k 10x mode 5x mode 1x mode temperature (c) C50 0 r on (m) 100 140 160 180 300 240 0 50 75 3577 g05 120 260 280 220 C25 25 100 125 i out = 400ma v bus = 4.5v v bus = 5.5v v bus = 5v temperature (c) C50 i bat (ma) 400 500 600 25 75 3577 g06 300 200 C25 0 50 100 125 100 0 v bus = 5v 10x mode r prog = 2k typical performance characteristics battery current and voltage vs time ltc3577 i bat vs v bat ltc3577-1 i bat vs v bat forward voltage vs ideal diode current (no external fet) forward voltage vs ideal diode current (with si2333ds external fet) t a = 25c unless otherwise speci? ed time (hour) 0 0 i bat (ma) v bat and v chrg (v) 100 200 300 400 600 1 234 3577 g07 56 500 0 1 2 3 4 6 v bat i bat c/10 5 1450mahr cell v bus = 5v r prog = 2k r clprog = 2k chrg safety timer termination v bat (v) 2.0 i bat (ma) 0 100 200 600 400 2.4 2.8 3.2 3.6 3577 g09 500 300 4.0 4.4 r clprog = 2.1k r prog = 2k v bus = 5v 10x mode falling v bat rising v bat v bat (v) 2.0 0 i bat (ma) 100 200 300 400 600 2.4 2.8 3.2 3.6 3577 g10 4.0 4.4 falling v bat 500 rising v bat r clprog = 2.1k r prog = 2k v bus = 5v 10x mode i bat (a) 0 0 v fwd (v) 0.05 0.10 0.15 0.20 0.25 0.2 0.4 0.6 0.8 3577 g11 1.0 1.2 v bat = 3.2v v bus = 0v t a = 25c v bat = 4.2v v bat = 3.6v i bat (a) 0 v fwd (mv) 15 20 25 0.6 1.0 3577 g12 10 5 0 0.2 0.4 0.8 30 35 40 v bat = 3.8v v bus = 0v t a = 25c battery regulation (float) voltage vs temperature temperature (c) C50 v bat (v) 4.22 25 3577 g08 4.12 4.14 4.08 C25 0 50 4.06 4.04 4.24 4.20 4.18 4.16 4.10 75 100 125 ltc3577 i bat = 2ma ltc3577-1
ltc3577/ltc3577-1 12 3577fa typical performance characteristics switching from suspend mode to 5x mode wall connect waveform wall disconnect waveform oscillator frequency vs temperature step-down switching regulator 1 3.3v output ef? ciency vs i out1 step-down switching regulator 2 1.8v output ef? ciency vs i out2 t a = 25c unless otherwise speci? ed ilim0 5v/div v out 5v/div i bus 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 100ma r clprog = 2k r prog = 2k ilim1 = 5v 100s/div 3577 g16 wall 5v/div v out 5v/div i wall 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 100ma r prog = 2k 1ms/div 3577 g17 wall 5v/div v out 5v/div i wall 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 100ma r prog = 2k 1ms/div 3577 g18 temperature (c) C50 1.5 f osc (mhz) 1.6 1.8 1.9 2.0 2.5 2.2 0 50 75 3577 g19 1.7 2.3 2.4 2.1 C25 25 100 125 v in = 5v v in = 3.8v v in = 2.7v v in = 2.9v i out (ma) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 100 1000 3577 g20 30 20 10 0 90 100 v in12 = 3.8v v in12 = 5v burst mode operation pulse-skipping mode v out1 = 3.3v i out (ma) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 100 1000 3577 g21 30 20 10 0 90 100 v in12 = 3.8v v in12 = 5v burst mode operation v out2 = 1.8v pulse-skipping mode input connect waveform input disconnect waveform switching from 1x to 5x mode v bus 5v/div v out 5v/div i bus 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 100ma r clprog = 2k r prog = 2k 1ms/div 3577 g13 v bus 5v/div v out 5v/div i bus 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 100ma r clprog = 2k r prog = 2k 1ms/div 3577 g14 ilim0/ilim1 5v/div i bus 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 50ma r clprog = 2k r prog = 2k 1ms/div 3577 g15
ltc3577/ltc3577-1 13 3577fa step-down switching regulator 3 1.2v output ef? ciency vs i out3 step-down switching regulator 3 2.5v output ef? ciency vs i out3 temperature (c) C50 short-circuit current (ma) 1100 25 3577 g24 800 600 C25 0 50 500 1200 1300 1400 1500 1000 900 700 75 100 125 800ma buck 500ma buck v inx = 3.8v v inx = 5v typical performance characteristics step-down switching regulator output transient (burst mode operation) step-down switching regulator output transient (pulse-skipping mode) 800ma step-down switching regulator feedback voltage vs output current t a = 25c unless otherwise speci? ed step-down switching regulator switch impedance vs temperature 500ma step-down switching regulator feedback voltage vs output current temperature (c) C50 0 switch impedance () 0.1 0.3 0.4 0.5 50 0.9 3577 g27 0.2 0 C25 75 100 25 125 0.6 0.7 0.8 800ma nmos 800ma pmos 500ma pmos 500ma nmos v inx = 3.2v output current (ma) 0.78 feedback (v) 0.84 0.85 0.77 0.76 0.83 0.80 0.82 0.81 0.79 0.1 10 100 1000 3577 g28 0.75 1 3.8v 5v burst mode operation pulse-skipping mode output current (ma) 0.78 feedback (v) 0.84 0.85 0.77 0.76 0.83 0.80 0.82 0.81 0.79 0.1 10 100 1000 3577 g29 0.75 1 3.8v 5v burst mode operation pulse-skipping mode v out1 50mv/div (ac) v out2 50mv/div (ac) v out3 100mv/div (ac) i out3 500ma 5ma 3577 g25 50s/div v out1 = 3.3v i out1 = 10ma v out2 = 1.8v i out2 = 20ma v out3 = 1.2v v out = v bat = 3.8v v out1 50mv/div (ac) v out2 50mv/div (ac) v out3 100mv/div (ac) i out3 500ma 5ma 3577 g26 50s/div v out1 = 3.3v i out1 = 30ma v out2 = 1.8v i out2 = 20ma v out3 = 1.2v v out = v bat = 3.8v ldo load step ldo1 50mv/div (ac) ldo2 20mv/div (ac) i out1 100ma 5ma 3577 g30 20s/div ldo1 = 1.2v ldo2 = 2.5v i ldo2 = 40ma v out = v bat = 3.8v step-down switching regulator short-circuit current vs temperature i out (ma) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 100 1000 3577 g22 30 20 10 0 90 100 v in3 = 3.8v v in3 = 5v burst mode operation v out3 = 1.2v pulse-skipping mode i out (ma) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 100 1000 3577 g23 30 20 10 0 90 100 v in3 = 3.8v v in3 = 5v burst mode operation v out3 = 2.5v pulse-skipping mode
ltc3577/ltc3577-1 14 3577fa typical performance characteristics ovsens quiescent current vs temperature ovgate vs ovsens input and battery current vs load current t a = 25c unless otherwise speci? ed rising overvoltage threshold vs temperature led driver ef? ciency 10 leds led driver ef? ciency 8 leds temperature (c) C40 quiescent current (a) 33 35 37 60 3577 g34 31 29 27 C15 10 35 85 v ovsens = 5v temperature (c) C40 opv threshold (v) 6.270 6.275 6.280 60 3577 g35 6.265 6.260 6.255 C15 10 35 85 input voltage (v) 0 0 ovgate (v) 2 4 6 8 10 12 24 68 3577 g36 ovsens connected to input through 6.2k resistor i load (ma) 0 600 500 400 300 200 100 0 C100 300 500 3577 g37 100 200 400 600 current (ma) i load i in i bat (charging) i bat (discharging) wall = 0v r prog = 2k r clprog = 2k i led (ma) 0 efficiency (%) 90 85 80 75 70 65 60 55 50 16 3577 g38 4 8 12 20 14 2 6 10 18 3v 3.6v 4.2v 4.8v 5.5v i led (ma) 0 efficiency (%) 90 85 80 75 70 65 60 55 50 16 35773 g39 4 8 12 20 14 2 6 10 18 3v 3.6v 4.2v 4.8v 5.5v ovp connection waveform ovp reconnection waveform ovp protection waveform v bus 5v/div ovgate 5v/div 500s/div 3577 g31 ovp input voltage 0v to 5v step 5v/div v bus 5v/div ovgate 5v/div 500s/div 3577 g32 ovp input voltage 5v to 10v step 5v/div v bus 5v/div ovgate 5v/div 500s/div 3577 g33 ovp input voltage 10v to 5v step 5v/div
ltc3577/ltc3577-1 15 3577fa led driver ef? ciency 6 leds led driver ef? ciency 4 leds typical performance characteristics t a = 25c unless otherwise speci? ed led pwm vs constant current ef? ciency too hot bat discharge dac code vs led current led boost start-up transient led boost maximum duty cycle vs temperature i led (ma) 0 efficiency (%) 90 85 80 75 70 65 60 55 50 16 3577 g40 4 8 12 20 14 2 6 10 18 3v 3.6v 4.2v 4.8v 5.5v i led (ma) 0 efficiency (%) 90 85 80 75 70 65 60 55 50 16 3577 g41 4 8 12 20 14 2 6 10 18 3v 3.6v 4.2v 4.8v 5.5v dac code 0 40 50 70 30 50 3577 g43 30 20 10 20 40 60 70 10 0 60 current (db) 60db = 20ma 0db = 20a r led_fs = 20k v bat (v) 3.8 0 i bat (ma) 20 60 80 100 200 140 3.9 4.0 3577 g48 40 160 180 120 4.1 4.2 v ntc < v too_hot v bus = 0v led boost current limit vs temperature temperature (c) C40 current limit (ma) 600 800 1000 1200 40 3577 g42 400 200 500 700 900 1100 300 100 0 C20 0 20 60 80 100 120 i led 10ma/div v boost 20v/div i l 200ma/div 2ms/div 3577 g44 temperature (c) C50 95.7 max duty cycle (%) 95.8 96.0 96.1 96.2 50 96.6 3577 g45 95.9 0 C25 75 100 25 125 96.3 96.4 96.5 3v 3.6v 4.2v 5.5v led current (a) 20 efficiency (%) 30 50 60 80 90 1.e-06 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 3577 g46 10 70 40 0 max pwm constant current battery discharge vs temperature temperature (c) 50 battery discharge current (ma) 175 80 3577 g47 100 50 60 70 90 25 0 200 150 125 75 100 110 120 v bus = 5v v bus = 0v v bat = 4.1v v ntc < v too_hot 5x mode i vout = 0ma
ltc3577/ltc3577-1 16 3577fa pin functions i lim0 , i lim1 (pins 1, 2): input current control pins. i lim0 and i lim1 control the input current limit. see table 1 in the usb powerpath controller section. both pins are pulled low by a weak current sink. led_fs (pin 3): a resistor between this pin and ground sets the full-scale output current of the i led pin. wall (pin 4): wall adapter present input. pulling this pin above 4.3v will disconnect the power path from v bus to v out . the acpr pin will also be pulled low to indicate that a wall adapter has been detected. sw3 (pin 5): power transmission (switch) pin for step- down switching regulator 3 (buck3). v in3 (pin 6): power input for step-down switching regula- tor 3. this pin should be connected to v out . fb3 (pin 7): feedback input for step-down switching regulator 3 (buck3). this pin servos to a ? xed voltage of 0.8v when the control loop is complete. ovsense (pin 8): overvoltage protection sense input. ovsense should be connected through a 6.2k resistor to the input power connector and the drain of an external n-channel mos pass transistor. when the voltage on this pin exceeds a preset level, the ovgate pin will be pulled to gnd to disable the pass transistor and protect downstream circuitry. led_ov (pin 9): a resistor between this pin and the boosted led backlight voltage sets the overvoltage limit on the boost output. if the boost voltage exceeds the programmed limit the led boost converter will be disabled. dv cc (pin 10): supply voltage for i 2 c lines. this pin sets the logic reference level of the ltc3577. a uvlo circuit on the dv cc pin forces all registers to all 0s whenever dv cc is <1v. bypass to gnd with a 0.1f capacitor. sda (pin 11): i 2 c data input. serial data is shifted one bit per clock to control the ltc3577. the logic level for sda is referenced to dv cc . scl (pin 12): i 2 c clock input. the logic level for scl is referenced to dv cc . ovgate (pin 13): overvoltage protection gate output. connect ovgate to the gate pin of an external n-channel mos pass transistor. the source of the transistor should be connected to v bus and the drain should be connected to the products dc input connector. in the absence of an overvoltage condition, this pin is connected to an internal charge pump capable of creating suf? cient overdrive to fully enhance this transistor. if an overvoltage condition is detected, ovgate is brought rapidly to gnd to prevent damage. ovgate works in conjunction with ovsense to provide this protection. pwr_on (pin 14): logic input used to keep buck dc/dcs enabled after power-up. may also be used to enable the buck dc/dcs directly (sequence = buck1 buck2 buck3). see the pushbutton interface opera- tion section for more information. on (pin 15): pushbutton input. a weak internal pull-up forces on high when left ? oating. a normally open push- button is connected from on to ground to force a low state on this pin. pbstat (pin 16): open-drain output is a de-bounced and buffered version of on to be used for processor interrupts. wake (pin 17): open-drain output. the wake pin indicates the operating state of the buck dc/dcs. if wake is hi-z, the buck dc/dcs are enabled and either up or powering up. a low on wake indicates that the buck dc/dcs are either powered down or are powering down. see the pushbutton interface operation section for more information. sw (pins 18,19,20): power transmission (switch) pin for led boost converter. see the led backlight/boost operation section for circuit hook-up and component selection. i 2 c is used to control led driver enable. i 2 c default is led driver off. pg_dcdc (pin 21): open-drain output. pg_dcdc goes high impedance 230ms after all buck dc/dcs are in regula- tion (within 8% of ? nal value).
ltc3577/ltc3577-1 17 3577fa pin functions i led (pin 22): series led backlight current sink output. this pin is connected to the cathode end of the series led backlight string. the current drawn through the series leds can be programmed via a 6-bit 60db dac and dimmed via an internal 4-bit pwm function. i 2 c is used to control led driver enable, brightness, gradation (soft on/soft off). i 2 c default is led driver off, current = 0ma. v inldo1 (pin 23): input supply of low dropout linear regulator 1 (ldo1). this pin should be bypassed to ground with a 1f or greater ceramic capacitor. ldo2_fb (pin 24): feedback voltage input for low drop- out linear regulator 2 (ldo2). ldo2 output voltage is set using an external resistor divider between ldo2 and ldo2_fb. fb2 (pin 25): feedback input for step-down switching regulator 2 (buck2). this pin servos to a ? xed voltage of 0.8v when the control loop is complete. fb1 (pin 26): feedback input for step-down switching regulator 1 (buck1). this pin servos to a ? xed voltage of 0.8v when the control loop is complete. ldo1_fb (pin 27): feedback voltage input for low drop- out linear regulator 1 (ldo1). ldo1 output voltage is set using an external resistor divider between ldo1 and ldo1_fb. ldo1 (pin 28): output of low dropout linear regulator 1. this pin must be bypassed to ground with a 1f or greater ceramic capacitor. ldo2 (pin 29): output of low dropout linear regulator 2. this pin must be bypassed to ground with a 1f or greater ceramic capacitor. v inldo2 (pin 30): input supply of low dropout linear regulator 2 (ldo2). this pin should be bypassed to ground with a 1f or greater ceramic capacitor. sw2 (pin 31): power transmission (switch) pin for step- down switching regulator 2 (buck2). v in12 (pin 32): power input for step-down switching regulators 1 and 2. this pin will generally be connected to v out . sw1 (pin 33): power transmission (switch) pin for step- down switching regulator 1 (buck1). ntcbias (pin 34): output bias voltage for ntc. a resistor from this pin to the ntc pin will bias the ntc thermistor. ntc (pin 35): the ntc pin connects to a batterys therm- istor to determine if the battery is too hot or too cold to charge. if the batterys temperature is out of range, charging is paused until it drops back into range. a low drift bias resistor is required from ntcbias to ntc and a thermistor is required from ntc to ground. prog (pin 36): charge current program and charge current monitor pin. connecting a resistor from prog to ground programs the charge current: i chg = 1000v r prog a () if suf? cient input power is available in constant current mode, this pin servos to 1v. the voltage on this pin always represents the actual charge current. idgate (pin 37): ideal diode gate connection. this pin controls the gate of an optional external p-channel mosfet transistor used to supplement the internal ideal diode. the source of the p-channel mosfet should be connected to v out and the drain should be connected to bat. it is important to maintain high impedance on this pin and minimize all leakage paths. bat (pin 38): single cell li-ion battery pin. depending on available power and load, a li-ion battery on bat will either deliver system power to v out through the ideal diode or be charged from the battery charger. v out (pin 39): output voltage of the powerpath controller and input voltage of the battery charger. the majority of the portable product should be powered from v out . the ltc3577 will partition the available power between the external load on v out and the internal battery charger. priority is given to the external load and any extra power is used to charge the battery. an ideal diode from bat to v out ensures that v out is powered even if the load exceeds the allotted input current from v bus or if the v bus power source is removed. v out should be bypassed with a low impedance multilayer ceramic capacitor.
ltc3577/ltc3577-1 18 3577fa v bus (pin 40): usb input voltage. v bus will usually be connected to the usb port of a computer or a dc output wall adapter. v bus should be bypassed with a low imped- ance multilayer ceramic capacitor. acpr (pin 41): wall adapter present output (active low). a low on this pin indicates that the wall adapter input com- parator has had its input pulled above its input threshold (typically 4.3v). this pin can be used to drive the gate of an external p-channel mosfet to provide power to v out from a power source other than a usb port. v c (pin 42): high voltage buck regulator control pin. this pin can be used to drive the v c pin of an approved external high voltage buck switching regulator. the v c pin is designed to work with the lt ? 3480, lt3653 and lt3505. consult factory for additional approved high voltage buck regulators. see the external hv buck control through the vc pin section for operating information. clprog (pin 43): input current program and input current monitor pin. a resistor from clprog to ground determines the upper limit of the current drawn from the v bus pin (i.e., the input current limit). a precise fraction of the input current, h clprog , is sent to the clprog pin. the input powerpath delivers current until the clprog pin reaches 2v (10x mode), 1v (5x mode) or 0.2v (1x mode). therefore, the current drawn from v bus will be limited to an amount given by h clprog and r clprog . in usb applications the resistor r clprog should be set to no less than 2.1k. chrg (pin 44): open-drain charge status output. the chrg pin indicates the status of the battery charger. if chrg is high then the charger is near the ? oat voltage (charge current less than 1/10th programmed charge cur- rent) or charging is complete and charger is disabled. a low on chrg indicates that the charger is enabled. for more information see the charge status indication section. ground (exposed pad pin 45): the exposed package pad is ground and must be soldered to pcb ground for electrical contact and rated thermal performance. pin functions
ltc3577/ltc3577-1 19 3577fa block diagram + C 39 + C 15mv v out hrst uvlo ideal diode cc/cv charger wall detect 500ma, 2.25mhz buck regulator input current limit overtemp battery safety discharge overvoltage protecton battery temp monitor i lim logic i 2 c logic 40v led backlight boost converter 0.8v en pg 500ma, 2.25mhz buck regulator 0.8v en pg 800ma, 2.25mhz buck regulator 0.8v pg_dcdc en pg 0.8v 150ma ldo1 en 37 idgate 38 bat 32 v in12 36 prog 33 sw1 26 fb1 25 fb2 5 sw3 7 fb3 31 sw2 23 v inld01 6 v in3 28 21 dv cc 10 pbstat 16 sw 18,19,20 led_ov 21 ldo1 27 ldo1_fb 0.8v 150ma ldo2 en 30 v inld02 29 ldo2 24 45 ldo2_fb 3577 bd 230ms falling delay chrg 44 chrge status i led 22 led_fs 3 dac 0.8v gnd sda 11 scl 12 pwr_on 14 ntc 35 ntcbias 34 clprog 43 v bus ovsens 40 i lim1 2 i lim0 1 wake 17 on 15 push- button input 8 ovgate 13 wall 4 acpr 41 v c control v c 42
ltc3577/ltc3577-1 20 3577fa operation powerpath operation introduction the ltc3577 is a highly integrated power management ic that features: C powerpath controller C battery charger C ideal diode C input overvoltage protection C pushbutton controller C three step-down switching regulators C high voltage buck regulator v c controller C two low dropout linear regulators C 40v led backlight controller designed speci? cally for usb applications, the powerpath controller incorporates a precision input current limit which communicates with the battery charger to ensure that input current does not violate the usb average input current speci? cation. the ideal diode from bat to v out guarantees that ample power is always available to v out even if there is insuf? cient or absent power at v bus . the ltc3577 also has the ability to receive power from a wall adapter or other non-current-limited power source. such a power supply can be connected to the v out pin of the ltc3577 through an external device such as a power schottky or fet as shown in figure 1. the ltc3577 has the unique ability to use the output, which is powered by an external supply, to charge the battery while provid- ing power to the load. a comparator on the wall pin is con? gured to detect the presence of the wall adapter and shut off the connection to the usb. this prevents reverse conduction from v out to v bus when a wall adapter is pres- ent. the ltc3577 provides a v c output pin which can be used to drive the v c pin of an external high voltage buck switching regulator such as the lt3480, lt3653 or lt3505 to provide power to the v out pin. the v c control circuitry adjusts the regulation point of the switching regulator to + C + C + C + C 4.3v (rising) 3.2v (falling) 75mv (rising) 25mv (falling) enable usb current limit constant current constant voltage battery charger wall from ac adapter (or high voltage buck output) 4 v bus from usb 40 37 + C 15mv idgate bat 3577 f01 li-ion optional external ideal diode pmos bat ideal diode 38 39 v out v out v c optional control for high voltage buck regs lt3480, lt3481 or lt3505 41 acpr 42 + system load figure 1. simpli? ed powerpath block diagram
ltc3577/ltc3577-1 21 3577fa operation a small voltage above the bat pin voltage. this control method provides a high input voltage, high ef? ciency battery charger and powerpath function. the ltc3577 also includes a pushbutton input to control the three synchronous step-down switching regulators and system reset. the three 2.25mhz constant frequency current mode step-down switching regulators provide 500ma, 500ma and 800ma each and support 100% duty cycle operation as well as burst mode operation for high ef? ciency at light load. no external compensation compo- nents are required for the switching regulators. the onboard led backlight boost circuitry can drive up to 10 series leds and includes versatile digital dimming via the i 2 c input. the i 2 c input also controls two 150ma low dropout (ldo) linear regulators. all regulators can be programmed for a minimum output voltage of 0.8v and can be used to power a microcon- troller core, microcontroller i/o, memory or other logic circuitry. usb powerpath controller the input current limit and charge control circuits of the ltc3577 are designed to limit input current as well as control battery charge current as a function of i vout . v out drives the combination of the external load, the three step-down switching regulators, two ldos, led backlight and the battery charger. if the combined load does not exceed the programmed input current limit, v out will be connected to v bus through an internal 200m p-channel mosfet. if the combined load at v out exceeds the programmed input current limit, the battery charger will reduce its charge current by the amount necessary to enable the external load to be satis? ed while maintaining the programmed input current. even if the battery charge current is set to exceed the allowable usb current, the average input current usb speci? cation will not be violated. furthermore, load current at v out will always be prioritized and only excess available cur- rent will be used to charge the battery. the current out of the clprog pin is a fraction (1/h clprog ) of the v bus current. when a programming resistor is connected from clprog to gnd, the voltage on clprog represents the input current: i vbus = i busq + v clprog r clprog ?h clprog where i busq and h clprog are given in the electrical char- acteristics table. the input current limit is programmed by the i lim0 and i lim1 pins. the ltc3577 can be con? gured to limit input current to one of several possible settings as well as be deactivated (usb suspend). the input current limit will be set by the appropriate servo voltage and the resistor on clprog according to the following expression: i vbus = i busq + 0.2v r clprog ?h clprog 1x mode () i vbus = i busq + 1v r clprog ?h clprog 5x mode () i vbus = i busq + 2v r clprog ?h clprog 10x mode () under worst-case conditions, the usb speci? cation for average input current will not be violated with an r clprog resistor of 2.1k or greater. table 1 shows the available settings for the i lim0 and i lim1 pins: table 1. controlled input current limit i lim1 i lim0 i bus(lim) 0 0 100ma (1x) 0 1 1a (10x) 1 0 suspend 1 1 500ma (5x) notice that when i lim0 is high and i lim1 is low, the input current limit is set to a higher current limit for increased charging and current availability at v out . this mode is typically used when there is a higher power, non-usb source available at the v bus pin.
ltc3577/ltc3577-1 22 3577fa operation ideal diode from bat to v out the ltc3577 has an internal ideal diode as well as a con- troller for an optional external ideal diode. both the internal and the external ideal diodes respond quickly whenever v out drops below bat. if the load increases beyond the input current limit, additional current will be pulled from the battery via the ideal diodes. furthermore, if power to v bus (usb) or v out (external wall power or high voltage regulator) is removed, then all of the application power will be provided by the battery via the ideal diodes. the ideal diodes are fast enough to keep v out from dropping signi? cantly with just the recommended output capacitor (see figure 2). the ideal diode consists of a precision ampli- ? er that enables an on-chip p-channel mosfet whenever the voltage at v out is approximately 15mv (v fwd ) below the voltage at bat. the resistance of the internal ideal diode is approximately 200m. if this is suf? cient for the application, then no external components are neces- sary. however, if lower resistance is needed, an external p-channel mosfet can be added from bat to v out . the idgate pin of the ltc3577 drives the gate of the external p-channel mosfet for automatic ideal diode control. the source of the mosfet should be connected to v out and the drain should be connected to bat. capable of driving a 1nf load, the idgate pin can control an external p-channel mosfet having extremely low on-resistance. using the wall pin to detect the presence of an external power source the wall input pin can be used to identify the presence of an external power source (particularly one that is not subject to a ? xed current limit like the usb v bus input). typically, such a power supply would be a 5v wall adapter output or the low voltage output of a high voltage buck regulator (speci? cally, lt3480, lt3653 or lt3505). when the wall adapter output (or buck regulator output) is con- nected directly to the wall pin, and the voltage exceeds the wall pin threshold, the usb power path (from v bus to v out ) will be disconnected. furthermore, the acpr pin will be pulled low. in order for the presence of an external power supply to be acknowledged, both of the following conditions must be satis? ed: 1. the wall pin voltage must exceed approximately 4.3v. 2. the wall pin voltage must be greater than 75mv above the bat pin voltage. the input power path (between v bus and v out ) is re- enabled and the acpr pin is pulled high when either of the following conditions is met: 1. the wall pin voltage falls to within 25mv of the bat pin voltage. 2. the wall pin voltage falls below 3.2v. each of these thresholds is suitably ? ltered in time to prevent transient glitches on the wall pin from falsely triggering an event. external hv buck control through the v c pin the wall, acpr and v c pins can be used in conjunction with an external high voltage buck regulator such as the lt3480, lt3505 or lt3653 to provide power directly to the v out pin as shown in figures 3 to 5 (consult factory for complete list of approved high voltage buck regulators). when the wall pin voltage exceeds 4.3v, v c pin control circuitry is enabled and drives the v c pin of the lt3480, lt3505 or lt3653. the v c pin control circuitry is designed so that no compensation components are required on the v c node. the voltage at the v out pin is regulated to the larger of (bat + 300mv) or 3.6v as shown in figure 6. 4.0v 3.8v v out 3.6v 500ma C500ma 0 i bat i vout load 1a 0a 10s/div charge discharge 3577 f02 v bat = 3.8v v bus = 5v 5x mode c out = 10f figure 2. ideal diode transient response
ltc3577/ltc3577-1 23 3577fa operation v in 2 3 dfls240l 0.47f 22f c out v out up to 2a bat 3577 f03 li-ion si2333ds si2333ds (opt) 6.8h 4 5 6 7 nc nc 10 boost v c 42 4 41 39 37 38 ltc3577 wall acpr idgate v out bat run/ss 150k 40.2k 68nf 4.7f hv in 8v to 38v (transients to 60v) 499k 100k sw r t 1 bd 8 11 9 fb lt3480 lt3480 high voltage buck circuitry gnd v c + figure 3. lt3480 buck control using v c (800khz switching) v in r t 1 2 mbrm140 0.1f 10f c out up to 1.2a v out bat 3577 f04 li-ion si2333ds si2333ds (opt) 6.8h 1n4148 3 4 6 boost v c 42 4 41 39 37 38 ltc3577 wall acpr idgate v out bat shdn 150k 806k bzt52c16t 20k 68nf 1f hv in 8v to 36v 49.9k 10.0k sw 7 5, 9 8 fb lt3505 lt3505 high voltage buck circuitry gnd v c + figure 4. lt3505 buck control using v c (2.2mhz switching with frequency foldback)
ltc3577/ltc3577-1 24 3577fa operation v in i lim i sense 7 8 dfls240l 0.1f 10v c out up to 1.2a v out bat 3577 f05 li-ion si2333ds (opt) 4.7h 1 4 9 boost v c 42 4 41 39 37 38 ltc3577 wall acpr idgate v out bat 324k 4.7f 60v hv in 7.5v to 30v (transients to 60v) sw 5 6 2 3 v out lt3653 high voltage buck circuitry gnd v c hvok + figure 5. lt3653 buck control using v c bat (v) 2.5 v out (v) 3.5 4.0 4.5 3577 f06 3.0 2.5 3 3.5 4 5.0 4.5 i o = 0.0a i o = 0.75a i o = 1.5a bat figure 6. v out voltage vs battery voltage (lt3480) bat (v) 2.5 v out (v) 3.5 4.0 4.5 3577 f07 3.0 2.5 3 3.5 4 5.0 4.5 i o = 0.0a i o = 0.6a bat figure 7. v out voltage vs battery voltage (lt3505)
ltc3577/ltc3577-1 25 3577fa operation the feedback network of the high voltage buck regulator should be set to generate an output voltage higher than 4.4v (be sure to include the output voltage tolerance of the buck regulator). the v c control of the ltc3577 overdrives the local v c control of the external high volt- age buck. therefore, once the v c control is enabled, the output voltage is set independent of the buck regulator feedback network. this technique provides a signi? cant ef? ciency advantage over the use of a 5v buck to drive the battery charger. with a simple 5v buck output driving v out , battery charger ef? ciency is approximately: charger = buck ? v bat 5v where buck is the ef? ciency of the high voltage buck regulator and 5v is the output voltage of the buck regu- lator. with a typical buck ef? ciency of 87% and a typical battery voltage of 3.8v, the total battery charger ef? ciency is approximately 66%. assuming a 1a charge current, this works out to nearly 2w of power dissipation just to charge the battery! with the v c control technique, battery charger ef? ciency is approximately: charger = buck ? v bat 0.3v + v bat with the same assumptions as above, the total battery charger ef? ciency is approximately 81%. this example works out to just 900mw of power dissipation. for applica- tions, component selection and board layout information beyond those listed here please refer to the respective high voltage buck regulator data sheet. suspend mode when i lim0 is pulled low and i lim1 is pulled high the ltc3577 enters suspend mode to comply with the usb speci? cation. in this mode, the power path between v bus and v out is put in a high impedance state to reduce the v bus input current to 50a. if no other power source is available to drive wall and v out , the system load connected to v out is supplied through the ideal diodes connected to bat. v bus undervoltage lockout (uvlo) and undervoltage current limit (uvcl) an internal undervoltage lockout circuit monitors v bus and keeps the input current limit circuitry off until v bus rises above the rising uvlo threshold (3.8v) and at least 50mv above v out . hysteresis on the uvlo turns off the input current limit if v bus drops below 3.7v or 50mv below v out . when this happens, system power at v out will be drawn from the battery via the ideal diode. to minimize the possibility of oscillation in and out of uvlo when using resistive input supplies, the input current limit is reduced as v bus falls below 4.45v (typ). battery charger the ltc3577 includes a constant-current/constant-volt- age battery charger with automatic recharge, automatic termination by safety timer, low voltage trickle charging, bad cell detection and thermistor sensor input for out of temperature charge pausing. when a battery charge cycle begins, the battery charger ? rst determines if the battery is deeply discharged. if the battery voltage is below v trkl , typically 2.85v, an automatic trickle charge feature sets the battery charge current to 10% of the programmed value. if the low voltage persists for more than one-half hour, the battery charger automatically terminates. once the battery voltage is above 2.85v, the battery charger begins charging in full power constant current mode. the current delivered to the battery will try to reach 1000v/r prog . depending on available input power and external load conditions, the battery charger may or may not be able to charge at the full programmed rate. the external load will always be prioritized over the battery charge current. the usb cur- rent limit programming will always be observed and only additional current will be available to charge the battery. when system loads are light, battery charge current will be maximized. charge termination the battery charger has a built-in safety timer. when the battery voltage approaches the ? oat voltage, the charge current begins to decrease as the ltc3577 enters constant voltage mode. once the battery charger detects that it has entered constant voltage mode, the four hour safety
ltc3577/ltc3577-1 26 3577fa operation timer is started. after the safety timer expires, charging of the battery will terminate and no more current will be delivered. automatic recharge after the battery charger terminates, it will remain off drawing only microamperes of current from the battery. if the portable product remains in this state long enough, the battery will eventually self discharge. to ensure that the battery is always topped off, a charge cycle will automati- cally begin when the battery voltage falls below v rechrg (typically 4.0v for ltc3577-1 and 4.1v for ltc3577). in the event that the safety timer is running when the battery voltage falls below v rechrg , the timer will reset back to zero. to prevent brief excursions below v rechrg from re- setting the safety timer, the battery voltage must be below v rechrg for more than 1.3ms. the charge cycle and safety timer will also restart if the v bus uvlo cycles low and then high (e.g., v bus , is removed and then replaced). charge current the charge current is programmed using a single resistor from prog to ground. 1/1000th of the battery charge cur- rent is delivered to prog which will attempt to servo to 1.000v . thus, the battery charge current will try to reach 1000 times the current in the prog pin. the program resistor and the charge current are calculated using the following equations: r prog = 1000v i chg , i chg = 1000v r prog in either the constant-current or constant-voltage charging modes, the prog pin voltage will be proportional to the actual charge current delivered to the battery. therefore, the actual charge current can be determined at any time by monitoring the prog pin voltage and using the fol- lowing equation: i bat = v prog r prog ? 1000 in many cases, the actual battery charge current, i bat , will be lower than i chg due to limited input current available and prioritization with the system load drawn from v out . thermal regulation to prevent thermal damage to the ic or surrounding components, an internal thermal feedback loop will automatically decrease the programmed charge current if the die temperature rises to approximately 110c. thermal regulation protects the ltc3577 from excessive temperature due to high power operation or high ambient thermal conditions and allows the user to push the limits of the power handling capability with a given circuit board design without risk of damaging the ltc3577 or external components. the bene? t of the ltc3577 thermal regula- tion loop is that charge current can be set according to actual conditions rather than worst-case conditions with the assurance that the battery charger will automatically reduce the current in worst-case conditions. charge status indication the chrg pin indicates the status of the battery charger. an open-drain output, the chrg pin can drive an indicator led through a current limiting resistor for human interfacing or simply a pull-up resistor for microprocessor interfacing. when charging begins, chrg is pulled low and remains low for the duration of a normal charge cycle. when charg- ing is complete, i.e., the charger enters constant voltage mode and the charge current has dropped to one-tenth of the programmed value, the chrg pin is released (high impedance). the chrg pin does not respond to the c/10 threshold if the ltc3577 is in input current limit. this prevents false end-of-charge indications due to insuf? cient power available to the battery charger. even though charg- ing is stopped during an ntc fault, the chrg pin will stay low indicating that charging is not complete. battery charger stability considerations the ltc3577s battery charger contains both a constant- voltage and a constant-current control loop. the constant- voltage loop is stable without any compensation when a battery is connected with low impedance leads. excessive lead length, however, may add enough series inductance to require a bypass capacitor of at least 1f from bat to gnd. furthermore, a 4.7f capacitor in series with a 0.2 to 1 resistor from bat to gnd is required to keep ripple voltage low when the battery is disconnected.
ltc3577/ltc3577-1 27 3577fa operation high value, low esr multilayer ceramic chip capacitors reduce the constant-voltage loop phase margin, possibly resulting in instability. ceramic capacitors up to 22f may be used in parallel with a battery, but larger ceramics should be decoupled with 0.2 to 1 of series resistance. in constant-current mode, the prog pin is in the feed- back loop rather than the battery voltage. because of the additional pole created by any prog pin capacitance, capacitance on this pin must be kept to a minimum. with no additional capacitance on the prog pin, the battery charger is stable with program resistor values as high as 25k. however, additional capacitance on this node reduces the maximum allowed program resistor. the pole frequency at the prog pin should be kept above 100khz. therefore, if the prog pin has a parasitic capacitance, c prog , the following equation should be used to calculate the maximum resistance value for r prog : r prog 1 2 ? 100khz ? c prog ntc thermistor and battery voltage reduction the battery temperature is measured by placing a nega- tive temperature coef? cient (ntc) thermistor close to the battery pack. to use this feature connect the ntc thermistor, r ntc , between the ntc pin and ground and a bias resistor, r nom , from ntcbias to ntc. r nom should be a 1% resistor with a value equal to the value of the chosen ntc thermistor at 25c (r25). the ltc3577 will pause charging when the resistance of the ntc thermistor drops to 0.54 times the value of r25 or approximately 54k (for a vishay curve 1 thermistor, this corresponds to approximately 40c). if the battery charger is in constant voltage (? oat) mode, the safety timer also pauses until the thermistor indicates a return to a valid temperature. as the temperature drops, the resistance of the ntc thermistor rises. the ltc3577 is also designed to pause charging when the value of the ntc thermistor increases to 3.17 times the value of r25. for a vishay curve 1 thermistor this resistance, 317k, corresponds to approximately 0c. the hot and cold comparators each have approximately 3c of hysteresis to prevent oscillation about the trip point. the typical ntc circuit is shown in figure 8. to improve safety and reliability the battery voltage is re- duced when the battery temperature becomes excessively high. when the resistance of the ntc thermistor drops to about 0.35 times the value of r25 or approximately 35k (for a vishay curve 1 thermistor, this corresponds to approximately 50c) the ntc enables circuitry to moni- tor the battery voltage. if the battery voltage is above the battery discharge threshold (about 3.9v) then the battery discharge circuitry is enabled and draws about 140ma from the battery when v bus = 0v and about 180ma when v bus = 5v. as the battery voltage approaches the discharge threshold the discharge current is linearly reduced until it reaches 0ma at which point the discharge circuitry is disabled. reducing the discharge current in this fashion keeps the circuit from causing oscillations on v bat due to battery esr. when the charger is disabled an internal watchdog timer samples the ntc thermistor for about 150s every 150ms and will enable the battery monitoring circuitry if the bat- tery temperature exceeds the ntc too_hot threshold. if adding a capacitor to the ntc pin for ? ltering the time constant must be much less than 150s so that the ntc pin can settle to its ? nal value during the sampling period. a time constant of less than 10s is recommended. once the battery monitoring circuitry is enabled it will remain enabled and monitoring the battery voltage until the battery C + C + r nom 100k r ntc 100k ntc ntcbias 34 0.26 ? ntcbias battery overtemp 3577 f08 ntc block ltc3577 too_cold too_hot 0.76 ? ntcbias 0.35 ? ntcbias C + 35 figure 8. typical ntc thermistor circuit
ltc3577/ltc3577-1 28 3577fa operation temperature falls back below the discharge temperature threshold. the battery discharge circuitry is only enabled if the battery voltage is greater than the battery discharge threshold. alternate ntc thermistors and biasing the ltc3577 provides temperature quali? ed charging if a grounded thermistor and a bias resistor are connected to ntc. by using a bias resistor whose value is equal to the room temperature resistance of the thermistor (r25) the upper and lower temperatures are pre-programmed to approximately 40c and 0c, respectively (assuming a vishay curve 1 thermistor). the upper and lower temperature thresholds can be ad- justed by either a modi? cation of the bias resistor value or by adding a second adjustment resistor to the circuit. if only the bias resistor is adjusted, then either the upper or the lower threshold can be modi? ed but not both. the other trip point will be determined by the characteristics of the thermistor. using the bias resistor in addition to an adjustment resistor, both the upper and the lower tempera- ture trip points can be independently programmed with the constraint that the difference between the upper and lower temperature thresholds cannot decrease. examples of each technique follows. ntc thermistors have temperature characteristics which are indicated on resistance-temperature conversion tables. the vishay-dale thermistor nths0603n011-n1003f, used in the following examples, has a nominal value of 100k and follows the vishay curve 1 resistance-temperature characteristic. in the following explanation, this notation is used. r25 = value of the thermistor at 25c r ntc|cold = value of thermistor at the cold trip point r ntc|hot = value of the thermistor at the hot trip point r cold = ratio of r ntc|cold to r25 r hot = ratio of r ntc|hot to r25 r nom = primary thermistor bias resistor (see figure 9) r1 = optional temperature range adjustment resistor (see figure 9) the trip points for the ltc3577s temperature quali? ca- tion are internally programmed at 0.35 ? v ntc for the hot threshold and 0.76 ? v ntc for the cold threshold. therefore, the hot trip point is set when: r ntc|hot r nom + r ntc|hot ? ntcbias = 0.35 ? ntcbias and the cold trip point is set when: r ntc|cold r nom + r ntc|cold ? ntcbias = 0.76 ? ntcbias solving these equations for r ntc|cold and r ntc|hot results in the following: r ntc|hot = 0.538 ? r nom and r ntc|cold = 3.17 ? r nom by setting r nom equal to r25, the above equations result in r hot = 0.538 and r cold = 3.17. referencing these ratios to the vishay resistance-temperature curve 1 chart gives a hot trip point of about 40c and a cold trip point of about 0c. the difference between the hot and cold trip points is approximately 40c. C + C + r nom 105k r ntc 100k r1 12.7k ntc ntcbias 34 0.26 ? ntcbias battery overtemp 3577 f09 ntc block ltc3577 too_cold too_hot 0.76 ? ntcbias 0.35 ? ntcbias C + 35 figure 9. ntc thermistor circuit with additional bias resistor
ltc3577/ltc3577-1 29 3577fa operation by using a bias resistor, r nom , different in value from r25, the hot and cold trip points can be moved in either direc- tion. the temperature span will change somewhat due to the non-linear behavior of the thermistor. the following equations can be used to easily calculate a new value for the bias resistor: r nom = r hot 0.538 ?r25 r nom = r cold 3.17 ?r25 where r hot and r cold are the resistance ratios at the de- sired hot and cold trip points. note that these equations are linked. therefore, only one of the two trip points can be chosen, the other is determined by the default ratios designed in the ic. consider an example where a 60c hot trip point is desired. from the vishay curve 1 r-t characteristics, r hot is 0.2488 at 60c. using the above equation, r nom should be set to 46.4k. with this value of r nom , the cold trip point is about 16c. notice that the span is now 44c rather than the previous 40c. this is due to the decrease in temperature gain of the thermistor as absolute tem- perature increases. the upper and lower temperature trip points can be inde- pendently programmed by using an additional bias resistor as shown in figure 9. the following formulas can be used to compute the values of r nom and r1: r nom = r cold ?r hot 2.714 ?r25 r1 = 0.536 ? r nom ?r hot ?r25 for example, to set the trip points to 0c and 45c with a vishay curve 1 thermistor choose r nom = 3.266 ? 0.4368 2.714 ? 100k = 104.2k the nearest 1% value is 105k. r1 = 0.536 ? 105k C 0.4368 ? 100k = 12.6k the nearest 1% value is 12.7k. the ? nal solution is shown in figure 9 and results in an upper trip point of 45c and a lower trip point of 0c. overvoltage protection (ovp) the ltc3577 can protect itself from the inadvertent ap- plication of excessive voltage to v bus or wall with just two external components: an n-channel fet and a 6.2k resistor. the maximum safe overvoltage magnitude will be determined by the choice of the external nmos and its associated drain breakdown voltage. the overvoltage protection module consists of two pins. the ? rst, ovsens, is used to measure the externally applied voltage through an external resistor. the second, ovgate, is an output used to drive the gate pin of an external fet. the voltage at ovsens will be lower than the ovp input voltage by (i ovsens ? 6.2k) due to the ovp circuits qui- escent current. the ovp input will be 200mv to 400mv higher than ovsens under normal operating conditions. when ovsens is below 6v, an internal charge pump will drive ovgate to approximately 1.88 ? ovsens. this will enhance the n-channel fet and provide a low impedance connection to v bus or wall which will, in turn, power the ltc3577. if ovsens should rise above 6v (6.35v ovp input) due to a fault or use of an incorrect wall adapter, ovgate will be pulled to gnd, disabling the external fet to protect downstream circuitry. when the voltage drops below 6v again, the external fet will be re-enabled. in an overvoltage condition, the ovsens pin will be clamped at 6v. the external 6.2k resistor must be sized appropriately to dissipate the resultant power. for example, a 1/10w 6.2k resistor can have at most pmax ? 6.2k = 24v applied across its terminals. with the 6v at ovsens, the maximum overvoltage magnitude that this resistor can withstand is 30v. a 1/4w 6.2k resis- tor raises this value to 45v. the charge pump output on ovgate has limited output drive capability. care must be taken to avoid leakage on this pin, as it may adversely affect operation. dual input overvoltage protection it is possible to protect both v bus and wall from overvoltage damage with several additional components, as shown in figure 10. schottky diodes d1 and d2 pass the larger of v1 and v2 to r1 and ovsens. if either v1 or v2 exceeds 6v plus v f(schottky) , ovgate will be pulled to gnd and both the wall and usb inputs will be protected.
ltc3577/ltc3577-1 30 3577fa c1 d1 r1 mn2 mn1 d2 v1 v2 3577 f10 wall ovgate ltc3577 v bus ovsens figure 10. dual input overvoltage protection operation each input is protected up to the drain-source breakdown, bvdss, of mn1 and mn2. r1 must also be rated for the power dissipated during maximum overvoltage. see the overvoltage protection section for an explanation of this calculation. table 2 shows some nmos fets that are suitable for overvoltage protection. table 2. recommended overvoltage fets nmos fet bvdss r on package si1472dh 30v 82m sc70-6 si2302ads 20v 60m sot-23 si2306bds 30v 65m sot-23 si2316bds 30v 80m sot-23 irlml2502 20v 35m sot-23 reverse input voltage protection the ltc3577 can also be easily protected against the application of reverse voltage as shown in figure 10. d1 and r1 are necessary to limit the maximum vgs seen by mp1 during positive overvoltage events. d1s breakdown voltage must be safely below mp1s bvgs. the circuit shown in figure 11 offers forward voltage protection up to mn1s bvdss and reverse voltage protection up to mp1s bvdss. low dropout linear regulator operation ldo operation and voltage programming the ltc3577 contains two 150ma adjustable output ldo regulators. to enable the ldos write a 1 to the ldo1en and/or ldo2en i 2 c registers. the ldos can be disabled three ways: 1) write a 0 to the ldo1en and ldo2en registers; 2) bring dv cc below the dv cc undervoltage threshold; 3) enter the power-down pushbutton state. 0.8v r1 ldox output c out r2 3577 f12 mp v inldox gnd ldox_fb 1 0 ldox ldoxen figure 12. ldo application circuit the ldos are further disabled if v out falls below the v out uvlo threshold and cannot be enabled until the uvlo condition is removed. when disabled all ldo circuitry is powered off leaving only a few nanoamps of leakage current on the ldo supply. the ldo outputs are individually pulled to ground through internal resistors when disabled. the power good status bits of ldo1 and ldo2 are avail- able in i 2 c through the read-back registers pgldo[1] and pgldo[2] for ldo1 and ldo2 respectively. the power good comparators for both ldos are sampled when the i 2 c port receives the correct i 2 c read address. figure 12 shows the ldo application circuit. the full- scale output voltage for each ldo is programmed using a resistor divider from the ldo output (ldo1 or ldo2) connected to the feedback pins (ldo1_fb or ldo2_fb) such that: v ldox = 0.8v ? r1 r2 + 1 ? ? ? ? ? ? d1 c1 r2 6.2k r1 500k d1: 5.6v zener mp1: si2323ds, bvdss = 20v v bus positive protection up to bvdss of mn1 v bus negative protection up to bvdss of mp1 mn1 mp1 usb/wall adapter 3577 f11 v bus ovgate ltc3577 ovsens figure 11. dual polarity voltage protection
ltc3577/ltc3577-1 31 3577fa operation for stability, each ldo output must be bypassed to ground with a minimum 1f ceramic capacitor (c out ). ldo operating as a current limited switch the ldo can be used as a current limited switch by simply connecting the ldox_fb input to ground. in this case the ldox output will be pulled up to v inldox through the ldos internal current limit (about 300ma). enabling the ldo via the i 2 c interface effectively connects ldox and v inldox , while disabling the ldo disconnected ldox from v inldox . step-down switching regulator operation introduction the ltc3577 includes three 2.25mhz constant frequency current mode step-down switching regulators providing 500ma, 500ma and 800ma each. all step-down switch- ing regulators can be programmed for a minimum output voltage of 0.8v and can be used to power a microcontroller core, microcontroller i/o, memory or other logic circuitry. all step-down switching regulators support 100% duty cycle operation (low dropout mode) when the input volt- age drops very close to the output voltage and are also capable of burst mode operation for highest ef? ciencies at light loads. burst mode operation is individually select- able for each step-down switching regulator through the i 2 c register bits bk1brst, bk2brst and bk3brst. the step-down switching regulators also include soft-start to limit inrush current when powering on, short-circuit cur- rent protection, and switch node slew limiting circuitry to reduce emi radiation. no external compensation com- ponents are required for the switching regulators. the regulators are sequenced up and down together through the pushbutton interface (see the pushbutton interface section for more information). it is recommended that the step-down switching regulator input supplies (v in12 and v in3 ) be connected to the system supply pin (v out ). this is recommended because the undervoltage lockout circuit on the v out pin (v out uvlo) disables the step- down switching regulators when the v out voltage drops below the v out uvlo threshold. if driving the step-down switching regulator input supplies from a voltage other than v out the regulators should not be operated outside the speci? ed operating range as operation is not guaranteed beyond this range. output voltage programming figure 13 shows the step-down switching regulator ap- plication circuit. the full-scale output voltage for each step-down switching regulator is programmed using a resistor divider from the step-down switching regulator output connected to the feedback pins (fb1, fb2 and fb3) such that: v outx = 0.8v ? r1 r2 + 1 ? ? ? ? ? ? typical values for r1 are in the range of 40k to 1m. the capacitor c fb cancels the pole created by feedback resis- tors and the input capacitance of the fb pin and also helps to improve transient response for output voltages much greater than 0.8v. a variety of capacitor sizes can be used for c fb but a value of 10pf is recommended for most ap- plications. experimentation with capacitor sizes between 2pf and 22pf may yield improved transient response. pg_dcdc operation the pg_dcdc pin is an open-drain output used to indi- cate that all step-down switching regulators are enabled and have reached their ? nal regulation voltage. a 230ms delay is included from the time all switching regulators reach 92% of their regulation value to allow a system controller ample time to reset itself. pg_dcdc may be used as a power-on reset to a microprocessor powered by the step-down switching regulators. pg_dcdc is an 0.8v r1 l v outx c out c fb r2 3577 f13 mp mn en mode slew v in gnd fbx swx pwm control figure 13. step-down switching regulator application circuit
ltc3577/ltc3577-1 32 3577fa operation open-drain output and requires a pull-up resistor to an appropriate power source. optimally the pull-up resistor is connected to one of the step-down switching regulator output voltages so that power is not dissipated while the regulators are disabled. operating modes the step-down switching regulators include two possible operating modes to meet the noise/power needs of a variety of applications. in pulse-skipping mode, an internal latch is set at the start of every cycle, which turns on the main p-channel mosfet switch. during each cycle, a current comparator compares the peak inductor current to the output of an error ampli? er. the output of the current comparator resets the internal latch, which causes the main p-channel mosfet switch to turn off and the n-channel mosfet synchronous recti? er to turn on. the n-channel mosfet synchronous recti? er turns off at the end of the 2.25mhz cycle or if the current through the n-channel mosfet synchronous recti? er drops to zero. using this method of operation, the error ampli? er adjusts the peak inductor current to deliver the required output power. all necessary compensation is internal to the step-down switching regulator requiring only a single ceramic output capacitor for stability. at light loads in pulse-skipping mode, the inductor current may reach zero on each pulse which will turn off the n-channel mosfet synchronous recti? er. in this case, the switch node (sw1, sw2 or sw3) goes high impedance and the switch node voltage will ring. this is discontinuous operation, and is normal behavior for a switching regulator. at very light loads in pulse-skipping mode, the step-down switching regulators will automati- cally skip pulses as needed to maintain output regulation. at high duty cycle (v outx approaching v inx ) it is possible for the inductor current to reverse at light loads causing the stepped down switching regulator to operate continu- ously. when operating continuously, regulation and low noise output voltage are maintained, but input operating current will increase to a few milliamps. in burst mode operation, the step-down switching regula- tors automatically switch between ? xed frequency pwm operation and hysteretic control as a function of the load current. at light loads the step-down switching regulators control the inductor current directly and use a hysteretic control loop to minimize both noise and switching losses. while operating in burst mode operation, the output capacitor is charged to a voltage slightly higher than the regulation point. the step-down switching regulator then goes into sleep mode, during which the output capacitor provides the load current. in sleep mode, most of the switching regulators circuitry is powered down, helping conserve battery power. when the output voltage drops below a pre-determined value, the step-down switching regulator circuitry is powered on and another burst cycle begins. the sleep time decreases as the load current increases. beyond a certain load current point (about 1/4 rated output load current) the step-down switching regulators will switch to a low noise constant frequency pwm mode of operation, much the same as pulse-skip- ping operation at high loads. for applications that can tolerate some output ripple at low output currents, burst mode operation provides better ef- ? ciency than pulse-skipping at light loads. the step-down switching regulators allow mode transition on-the-? y, providing seamless transition between modes even under load. this allows the user to switch back and forth between modes to reduce output ripple or increase low current ef- ? ciency as needed. burst mode operation is individually selectable for each step-down switching regulator through the i 2 c register bits bk1brst, bk2brst and bk3brst. shutdown the step-down switching regulators are shut down when the pushbutton circuitry is in the power-down, power off or hard reset states. in shutdown all circuitry in the step-down switching regulator is disconnected from the switching regulator input supply leaving only a few nanoamps of leakage current. the step-down switching regulator outputs are individually pulled to ground through internal 10k resistors on the switch pin (sw1, sw2 or sw3) when in shutdown. dropout operation it is possible for a step-down switching regulators input voltage to approach its programmed output voltage (e.g., a battery voltage of 3.4v with a programmed output voltage of 3.3v). when this happens, the pmos switch duty cycle
ltc3577/ltc3577-1 33 3577fa operation increases until it is turned on continuously at 100%. in this dropout condition, the respective output voltage equals the regulators input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. soft-start operation soft-start is accomplished by gradually increasing the peak inductor current for each step-down switching regulator over a 500s period. this allows each output to rise slowly, helping minimize inrush current required to charge up the switching regulator output capacitor. a soft-start cycle occurs whenever a given switching regulator is enabled. a soft-start cycle is not triggered by changing operating modes. this allows seamless output transition when actively changing between operating modes. slew rate control the step-down switching regulators contain new patent pending circuitry to limit the slew rate of the switch node (sw1, sw2 and sw3). this new circuitry is designed to transition the switch node over a period of a few nanosec- onds, signi? cantly reducing radiated emi and conducted supply noise while maintaining high ef? ciency. since slowing the slew rate of the switch nodes causes ef? ciency loss, the slew rate of the step-down switching regulators is adjustable via the i 2 c registers slewctl1 and slewctl2. this allows the user to optimize ef? ciency or emi as neces- sary with four different slew rate settings. the power-up default is the fastest slew rate (highest ef? ciency) setting. figures 14 and 15 show the ef? ciency and power loss graph for buck3 programmed for 1.2v and 2.5v outputs. note that the power loss curves remain fairly constant for both graphs yet changing the slew rate has a larger effect on the 1.2v output ef? ciency. this is mainly because for a given output current the 2.5v output is delivering more than 2x the power than the 1.2v output. ef? ciency will always decrease and show more variation to slew rate as the programmed output voltage is decreased. low supply operation an undervoltage lockout circuit on v out (v out uvlo) shuts down the step-down switching regulators when v out drops below about 2.7v. it is recommended that the step- down switching regulator input supplies (v in12 , v in3 ) be connected to the power path output (v out ) directly. this uvlo prevents the step-down switching regulators from operating at low supply voltages where loss of regula- tion or other undesirable operation may occur. if driving the step-down switching regulator input supplies from a voltage other than the v out pin, the regulators should not be operated outside the speci? ed operating range as operation is not guaranteed beyond this range. inductor selection many different sizes and shapes of inductors are available from numerous manufacturers. choosing the right inductor from such a large selection of devices can be overwhelming, but following a few basic guidelines will make the selection figure 14. v out3 (1.2v) ef? ciency and power loss vs i out3 figure 15. v out3 (2.5v) ef? ciency and power loss vs i out3 i out3 (ma) 1.00e-05 efficiency (%) power loss (w) 60 80 100 1.00e-01 3577 f14 40 20 50 70 90 30 10 0 1.00e-02 1.00e-01 1.00e+00 1.00e-03 1.00e-04 1.00e-05 1.00e-0.3 burst mode operation v in = 3.8v sw[1:0] = 00 01 10 11 i out3 (ma) 1.00e-05 efficiency (%) power loss (w) 60 80 100 1.00e-01 3577 f15 40 20 50 70 90 30 10 0 1.00e-02 1.00e-01 1.00e+00 1.00e-03 1.00e-04 1.00e-05 1.00e-0.3 burst mode operation v in = 3.8v sw[1:0] = 00 01 10 11
ltc3577/ltc3577-1 34 3577fa operation process much simpler. the step-down switching regula- tors are designed to work with inductors in the range of 2.2h to 10h. for most applications a 4.7h inductor is suggested for step-down switching regulators providing up to 500ma of output current while a 3.3h inductor is suggested for step-down switching regulators providing up to 800ma. larger value inductors reduce ripple current, which improves output ripple voltage. lower value induc- tors result in higher ripple current and improved transient response time, but will reduce the available output current. to maximize ef? ciency, choose an inductor with a low dc resistance. for a 1.2v output, ef? ciency is reduced about 2% for 100m series resistance at 400ma load current, and about 2% for 300m series resistance at 100ma load current. choose an inductor with a dc current rating at least 1.5 times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. if output short-circuit is a possible condition, the inductor should be rated to handle the maximum peak current speci? ed for the step-down converters. different core materials and shapes will change the size/current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. inductors that are very thin or have a very small volume typically have much higher core and dcr losses, and will not give the best ef? ciency. the choice of which style inductor to use often depends more on the price versus size, performance, and any radiated emi requirements than on what the step-down switching regulators requires to operate. the inductor value also has an effect on burst mode operation. lower inductor values will cause burst mode switching frequency to increase. table 3 shows several inductors that work well with the step-down switching regulators. these inductors offer a good compromise in current rating, dcr and physical size. consult each manufacturer for detailed information on their entire selection of inductors. input/output capacitor selection low esr (equivalent series resistance) ceramic capacitors should be used at both step-down switching regulator outputs as well as at each step-down switching regulator input supply. only x5r or x7r ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. a 10f output capacitor is suf? cient for the step-down switching regulator outputs. for good transient response table 3. recommended inductors for step-down switching regulators inductor type l (h) max i dc (a) max dcr () size in mm (l w h) manufacturer db318c d312c de2812c 4.7 3.3 4.7 3.3 4.7 3.3 1.07 1.20 0.79 0.90 1.15 1.37 0.1 0.07 0.24 0.20 0.13* 0.105* 3.8 3.8 1.8 3.8 3.8 1.8 3.6 3.6 1.2 3.6 3.6 1.2 3.0 2.8 1.2 3.0 2.8 1.2 toko www.toko.com cdrh3d16 cdrh2d11 cls4d09 4.7 3.3 4.7 3.3 4.7 0.9 1.1 0.5 0.6 0.75 0.11 0.085 0.17 0.123 0.19 4 4 1.8 4 4 1.8 3.2 3.2 1.2 3.2 3.2 1.2 4.9 4.9 1 sumida www.sumida.com sd3118 sd3112 sd12 sd10 4.7 3.3 4.7 3.3 4.7 3.3 4.7 3.3 1.3 1.59 0.8 0.97 1.29 1.42 1.08 1.31 0.162 0.113 0.246 0.165 0.117* 0.104* 0.153* 0.108* 3.1 3.1 1.8 3.1 3.1 1.8 3.1 3.1 1.2 3.1 3.1 1.2 5.2 5.2 1.2 5.2 5.2 1.2 5.2 5.2 1.0 5.2 5.2 1.0 cooper www.cooperet.com lps3015 4.7 3.3 1.1 1.3 0.2 0.13 3.0 3.0 1.5 3.0 3.0 1.5 coil craft www.coilcraft.com *typical dcr
ltc3577/ltc3577-1 35 3577fa operation and stability the output capacitor for step-down switching regulators should retain at least 4f of capacitance over operating temperature and bias voltage. each switching regulator input supply should be bypassed with a 2.2f capacitor. consult with capacitor manufacturers for de- tailed information on their selection and speci? cations of ceramic capacitors. many manufacturers now offer very thin (<1mm tall) ceramic capacitors ideal for use in height-restricted designs. table 4 shows a list of several ceramic capacitor manufacturers. table 4. ceramic capacitor manufacturers avx www.avxcorp.com murata www.murata.com taiyo yuden www.t-yuden.com vishay siliconix www.vishay.com tdk www.tdk.com led backlight/boost operation introduction the led driver uses a constant frequency, current mode boost converter to supply power to up to 10 series leds. as shown in figure 16 the series string of leds is con- nected from the output of the boost converter (boost) to the i led pin. under normal operation the boost converter boost output will be driven to a voltage where the i led pin regulates at 300mv. the i led pin is a constant-current sink that is programmed via i 2 c led dac register. the led can be further controlled using i 2 c to program bright- ness levels and soft turn-on/turn-off effects. see the i 2 c interface section for more information on programming the i led current. the boost converter also includes an overvoltage protection feature to limit the boost output voltage as well as variable slew rate control of the sw pin to reduce emi. led boost operation the led boost converter is designed for very high duty cycle operation and can boost from 3v to 40v for load currents up to 20ma. the boost converter also features an overvoltage protection feature to protect the output in case of an open circuit in the led string. the overvoltage protection threshold is set by adjusting r1 in figure 16 such that: boost(max) = 800mv ? r1 10 ?r2 + led_ ov where led_ov is about 1.0v. in the case of figure 16 boost(max) is set to 40v for a 10-led string. capacitor c3 provides soft-start, limiting the inrush cur- rent when the boost converter is ? rst enabled. c3 provides feedback to the i led pin. this feedback limits the rise time of output voltage and the inrush current while the output capacitor, c2, is charging. the boost converter will be operated in either continuous conduction mode, discontinuous conduction mode or pulse-skipping mode depending on the inductor current required for regulation. c2 1f 50v c3 22nf 50v d12 zlls400 c1 22f r1 10m d1 r2 20k l1 10h lps4018-103ml 39 18 boost 19 20 3577 f16 v out 9 led_ov sw sw 3 22 i led_fs i led sw ltc3577 d2 d3 d4 d5 d10 d9 d8 d7 d6 figure 16. led boost application circuit led constant current sink the led driver uses a precision current sink to regulate the led current up to 20ma. the current sink is programmed via i 2 c led dac register and utilizes a 6-bit 60db expo- nential dac. this dac provides accurate current control from 20a to 20ma with approximately 1db per step for i led(fs) = 20ma. the led current can be approximated by the following equations: i led = i led(fs) ?10 3 ? dac ? 63 63 ? ? ? ? ? ? i led(fs) = 0.8v r2 ? 500 (1)
ltc3577/ltc3577-1 36 3577fa operation where dac is the decimal value programmed into the i 2 c led dac register. for example with i led(fs) = 20ma and dac[5:0] = 000000 (0 decimal) i led equates to 20a, while dac[5:0] = 111111 (63 decimal) i led equates to 20ma. as a ? nal example dac[5:0] = 101010 is 42 decimal and equates to i led = 2ma for i led(fs) = 20ma. the dac approximates the equation 1 using the nominal values in table 5. the differences between the approximation equation and the table are due to design of the dac using eight linear seg- ments that approximate the exponential function. table 5. led dac codes to output current dac codes output current dac codes output current 0 20.0a 32 668a 1 23.5a 33 786a 2 27.0a 34 903a 3 30.5a 35 1.02ma 4 34.0a 36 1.14ma 5 37.6a 37 1.26ma 6 41.1a 38 1.37ma 7 44.6a 39 1.49ma 8 48.1a 40 1.61ma 9 56.5a 41 1.89ma 10 65.0a 42 2.17ma 11 73.4a 43 2.45ma 12 81.9a 44 2.74ma 13 90.3a 45 3.02ma 14 98.7a 46 3.30ma 15 107a 47 3.58ma 16 116a 48 3.86ma 17 136a 49 4.54ma 18 156a 50 5.22ma 19 177a 51 5.90ma 20 197a 52 6.58ma 21 217a 53 7.26ma 22 237a 54 7.93ma 23 258a 55 8.61ma 24 278a 56 9.29ma 25 327a 57 10.8ma 26 376a 58 12.4ma 27 424a 59 13.9ma 28 473a 60 15.4ma 29 522a 61 17.0ma 30 571a 62 18.5ma 31 620a 63 20.0ma the full-scale led current is set using a resistor (r2 in figure 16) connected between the led_fs pin and ground. typically r2 should be set to 20k to give 20ma of led current at full-scale. the resistance may be increased to decrease the current or the resistance may be decreased to increase the led current. the dac has been optimized for best performance at 20ma full-scale. the full-scale current may be adjusted but the accuracy of the output current will be degraded the further it is programmed from 20ma. the led_fs pin is current limited and will only source about 80a. this protects the pin and limits the i led current in a case where led_fs is shorted to ground, it is not recommended to program the led cur- rent above 25ma. led gradation the led driver features an automatic gradation circuit. the gradation circuit ramps the led current up when the led driver is enabled and ramps the current down when the led driver is disabled. the dac is enabled and disabled with the en bit of the i 2 c led control register. the gradation function is automatic when enabling and disabling the led driver; only the gradation speed needs to be programmed to use this function. the gradation speed is set by the gr1 and gr2 bits of the i 2 c led control register which allows transitions times of approximately 15ms, one-half second, one second and two seconds. see the i 2 c interface section for more information. the gradation function allows the leds to turn on and off gradually as opposed to an abrupt step. led pwm vs constant current operation the led driver provides both linear led current mode as well as pwm led current mode. these modes are selected through the md1 and md2 bits of the i 2 c led control register. when both bits are 0 the led boost converter is in constant current (cc) mode and the i led current sink is constant whose value is set by the dac[5:0] bits of the i 2 c led dac register. setting md1 to 0 and md2 to 1 selects the led pwm mode. in this mode the led driver is pulsed using an internally generated pwm signal. the pwm mode may be used to re- duce the led intensity for a given programmed current.
ltc3577/ltc3577-1 37 3577fa operation when dimming via pwm the led driver and boost converter are both turned on and off together. this allows some degree of additional control over the led current, and in some cases may offer a more ef? cient method of dimming since the boost could be operated at an optimal ef? ciency point and then pulsed for the desired led intensity. the pwm mode, if enabled, is set up using 3 values; pwmnum[3:0] and pwmden[3:0] in the i 2 c led pwm register and pwmclk, set by pwmc2 and pwmc1 in the i 2 c led control register. duty cycle = pwmnum pwmden frequency = pwmclk pwmden table 6. pwm clock frequency pwmc2 pwmc1 pwmclk 0 0 8.77khz 0 1 4.39khz 1 0 2.92khz 1 1 2.19khz using the pwm control, a 4-bit internally generated pwm is possible as additional dimming. using these control bits a number of pwm duty cycles and frequencies are available in the 100hz to 500hz range. this range was selected to be below the audio range and above the frequency where the pwm is visible. for example, given pwmc2 = 1, pwmc1 = 0, pwm- num[3:0] = 0111 and pwmden[3:0] = 1100 then the duty cycle will be 58.3% and pwm frequency will be 243hz. if pwmnum is set to 0 then the duty cycle will be 0% and the current sink will effectively be off. if pwmnum is programmed to a value larger than pwmden the duty cycle will be 100% and the current sink will effectively be constant. pwmden and pwmnum may both be changed to result in 73 different duty cycle possibilities and 41 dif- ferent pwm frequencies between 8.77khz and 100hz. when pwm mode is enabled, a small (2a) standby current source is always enabled on the i led pin. the purpose of this is to have some current ? owing in the leds at all times. this helps to reduce the magnitude of the voltage swing on the i led pin as the current is pulsed on and off. fixed boost output setting md1 to 1 and md2 to 0 selects the ? xed high voltage boost mode. this mode can be used to generate output voltages at or greater than v out . when con? gured as a boost converter the i led pin becomes the feedback pin, and will regulate the output voltage such that the voltage on the i led pin is 800mv. figure 17 shows a ? xed 12v output generated using the boost converter in the ? xed high voltage boost mode. any output voltage up to 40v may be programmed by select- ing appropriate values for the r1 and r2 voltage divider from the equation: v boost = 0.8v ? r1 r2 + 1 ? ? ? ? ? ? values for r2 should be kept below 24.3k to keep the pole at i led beyond cross over. the boost is designed primarily as a high voltage, high duty cycle converter. when operating with a lower boost ratio, a larger output capacitor, 10f, should be used. operating with a very low duty cycle will cause cycle skipping which will increase ripple. c2 10f 10v d12 zlls400 800mv v ref c1 22f r1 301k r2 21.5k l4 10h lps4018-103ml 39 3 18 boost 19 20 3577 f17 v out i led_fs 22 i led sw sw 9 led_ov sw ltc3577 figure 17. fixed 12v/75ma boost output application
ltc3577/ltc3577-1 38 3577fa operation to keep the average steady-state inductor current below 300ma the maximum output current is reduced as pro- grammed output voltage increases. the output current available is given by: i boost(max) = 300ma ? v out(min) v boost note that the maximum boost output current must be set by the minimum v out operating voltage. if the boost converter is allowed to operate down to the v out uvlo then 2.5v must be assumed as the minimum operating v out voltage. inductor selection the led boost converter is designed to work with a 10h inductor. the inductor must be able to handle a peak current of 1a and should have a low esr value for good ef? ciency. table 7 shows several inductors that work well with the led boost converter. these inductors offer a good compromise in current rating, dcr and physical size. consult each manufacturer for detailed information on their entire selection of inductors. diode selection when boosting to increasingly higher voltages, parasitic capacitance at the switch pin becomes an increasing large component of the switching loses. for this reason it is important to minimize the capacitance on the switch node. the diode selected should be sized to handle the peak inductor current and the average output current. at high boost voltages a diode with the lowest possible junction capacitance will often result in a more ef? cient solution than one with a lower forward drop. i 2 c operation i 2 c interface the ltc3577 may communicate with a bus master using the standard i 2 c 2-wire interface. the timing diagram shows the relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources, such as the ltc1694 smbus accelerator, are required on these lines. the ltc3577 is both a slave receiver and slave transmitter. the i 2 c control signals, sda and scl are scaled internally to the dv cc supply. dv cc should be connected to the same power supply as the bus pull-up resistors. the i 2 c port has an undervoltage lockout on the dv cc pin. when dv cc is below approximately 1v , the i 2 c serial port is cleared, the ltc3577 is set to its default con? guration of all zeros. table 7. recommended inductors for boost switching regulators inductor type l (h) max i dc (a) max dcr () size in mm (l w h) manufacturer db62lcb 10 1.22 0.118 6.2 6.2 2 toko www.toko.com cdrh4d16np-100m 10 10.5 0.155 4.8 4.8 1.8 sumida www.sumida.com sd18-100-r 10 1.28 0.158* 5.2 5.2 1.8 cooper www.cooperet.com lps4018-103 10 1.1 0.200 4.0 4.0 1.8 coil craft www.coilcraft.com *typical
ltc3577/ltc3577-1 39 3577fa operation i 2 c bus speed the i 2 c port is designed to be operated at speeds of up to 400khz. it has built-in timing delays to ensure correct operation when addressed from an i 2 c compliant master device. it also contains input ? lters designed to suppress glitches should the bus become corrupted. i 2 c start and stop conditions a bus master signals the beginning of communications by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. the master may transmit either the slave write or the slave read address. once data is written to the ltc3577, the master may transmit a stop condition which commands the ltc3577 to act upon its new command set. a stop condition is sent by the master by transitioning sda from low to high while scl is high. the bus is then free for communication with another i 2 c device. i 2 c byte format each byte sent to or received from the ltc3577 must be 8 bits long followed by an extra clock cycle for the acknowledge bit. the data should be sent to the ltc3577 most signi? cant bit (msb) ? rst. i 2 c acknowledge the acknowledge signal is used for handshaking between the master and the slave. when the ltc3577 is written to (write address), it acknowledges its write address as well as the subsequent two data bytes. when it is read from (read address), the ltc3577 acknowledges its read address only. the bus master should acknowledge receipt of information from the ltc3577. an acknowledge (active low) generated by the ltc3577 lets the master know that the latest byte of information was received. the acknowledge related clock pulse is generated by the master. the master releases the sda line (high) during the acknowledge clock cycle. the ltc3577 pulls down the sda line during the write acknowledge clock pulse so that it is a stable low during the high period of this clock pulse. when the ltc3577 is read from, it releases the sda line so that the master may acknowledge receipt of the data. since the ltc3577 only transmits one byte of data, a master not acknowledging the data sent by the ltc3577 has no i 2 c speci? c consequence on the operation of the i 2 c port. i 2 c timing diagram t su, dat t hd, sta t hd, dat sda scl t su, sta t hd, sta t su, sto 3577 td t buf t low t high start condition repeated start condition stop condition start condition t r t f t sp ack ack 123 address wr 456789123456789123456789 00 01 0 01 0 00010010 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 ack stop start sda scl data byte a data byte b
ltc3577/ltc3577-1 40 3577fa operation i 2 c slave address the ltc3577 responds to a 7-bit address which has been factory programmed to b0001001[r/w]. the lsb of the address byte, known as the read/write bit, should be 0 when writing data to the ltc3577 and 1 when reading data from it. considering the address an eight bit word, then the write address is 0x12 and the read address is 0x13. the ltc3577 will acknowledge both its read and write address. i 2 c sub-addressed writing the ltc3577 has four command registers for control input. they are accessed by the i 2 c port via a sub- addressed writing system. each write cycle of the ltc3577 consists of exactly three bytes. the ? rst byte is always the ltc3577s write address. the second byte represents the ltc3577s sub-address. the sub address is a pointer which directs the subsequent data byte within the ltc3577. the third byte consists of the data to be written to the location pointed to by the sub- address. the ltc3577 contains control registers at only four sub-address locations: 0x00, 0x01, 0x02 and 0x03. writing to sub-addresses outside the four sub-addresses listed is not recommended as it can cause data in one of the four listed sub-addresses to be overwritten. i 2 c bus write operation the master initiates communication with the ltc3577 with a start condition and the ltc3577s write address. if the address matches that of the ltc3577, the ltc3577 returns an acknowledge. the master should then deliver the sub-address. again the ltc3577 acknowledges and the cycle is repeated for the data byte. the data byte is transferred to an internal holding latch upon the return of its acknowledge by the ltc3577. this procedure must be repeated for each sub-address that requires new data. after one or more cycles of [address][sub-address][data], the master may terminate the communication with a stop condition. alternatively, a repeat-start condition can be initiated by the master and another chip on the i 2 c bus can be addressed. this cycle can continue inde? nitely and the ltc3577 will remember the last input of valid data that it received. once all chips on the bus have been addressed and sent valid data, a global stop can be sent and the ltc3577 will update its command latches with the data that it had received. i 2 c bus read operation the bus master reads the status of the ltc3577 with a start condition followed by the ltc3577 read address. if the read address matches that of the ltc3577, the ltc3577 returns an acknowledge. following the acknowledgement of its read address the ltc3577 returns one bit of status information for each of the next 8 clock cycles. a stop command is not required for the bus read operation. i 2 c input data there are 4 bytes of data that can be written to on the ltc3577. the bytes are accessed through the sub- addresses 0x00 to 0x03. at ? rst power application (v bus , wall or bat) all bits default to 0. additionally all bits are cleared to 0 when dv cc drops below its undervoltage lock out or if the pushbutton enters the power-down (pdn1 or pdn2) state. table 8. ldo and buck control register ldo and buck control register address: 00010010 sub-address: 00000000 bit name function b0 ldo1en enable ldo 1 b1 ldo2en enable ldo 2 b2 bk1brst buck1 burst mode enable b3 bk2brst buck2 burst mode enable b4 bk3brst buck2 burst mode enable b5 slewctl1 buck sw slew rate: 00 = 1ns, 01 = 2ns, 10 = 4ns, 11 = 8ns b6 slewctl2 b7 n/a not usedno effect on operation table 8 shows the ? rst byte of data that can be written to at sub-address 0x00. this byte of data is referred to as the ldo and buck control register. bits b0 and b1 enable and disable the ldos. writing 1 to b0 or b1 will enable ldo1 or ldo2 respectively, while writing a 0 will disable the respective ldo.
ltc3577/ltc3577-1 41 3577fa operation bits b2, b3, and b4 set the operating modes of the step- down switching regulators (bucks). writing 1 to any of these three registers will put that respective buck converter in the high ef? ciency burst mode operation, while a 0 will enable the low noise pulse-skipping mode operation. the b5 and b6 bits adjust the slew rate of all sw pins together so they all slew at the same rate. it is recom- mended that the fastest slew rate (b6:b5 = 00) be used unless emi is an issue in the application as slower slew rates cause reduced ef? ciency. table 9. i 2 c led control register led control register address: 00010010 sub-address: 00000001 bit name function b0 en enable: 1 = enable 0 = off b1 gr2 gradation gr[2:1]: 00 = 15ms, 01 = 460ms, 10 = 930ms, 11 = 1.85s b2 gr1 b3 md1 mode md[2:1]: 00 = cc boost, 10 = pwm boost; 01 = hv boost b4 md2 b5 pwmc1 pwm clk pwmc[2:1]: 00 = 8.77khz, 01 = 4.39khz, 10 = 2.92khz, 11 = 2.19khz b6 pwmc2 b7 slewled led sw slew rate: 0/1 = fast/slow table 9 shows the second byte of data that can be written to at sub-address 0x01. this byte of data is referred to as the led control register. bit b0 enables and disables the led boost circuitry. writing a 1 to b0 enables the led boost circuitry, while writing a 0 disables the led boost circuitry. bits b1 and b2 are the led gradation which sets the ramp up and down time of the led current when enabled or disabled. the gradation function allows the leds to turn on/off gradually as opposed to an abrupt step. bits b3 and b4 set the operating mode of the led boost circuitry. the operating modes are: b4:b3 = 00 led constant current (cc) boost operation; b4:b3 = 10 led pwm boost operation; b4:b3 = 01 ? xed high voltage (hv) output boost operation; b4:b3 = 11 not supported, do not use. see the led backlight/boost operation section for more information on the operating modes. bits b5 and b6 set the pwm clock speed as shown in table 9 of the led backlight/boost operation section. bit b7 sets the slew rate of the led boost sw pin. setting b7 to 0 results in the fastest slew rate and provides the most ef? cient mode of operation. setting b7 to 1 should only be used in cases where emi due to sw slewing is an issue as the slower slew rate causes a loss in ef? ciency. see the led backlight/boost operation section for more detailed operating information. table 10 shows the third byte of data that can be written to at sub-address 0x02. this byte of data is referred to as the led dac register. the led current source utilizes a 6-bit 60db exponential dac. this dac provides accurate current control from 20a to 20ma with approximately 1db per step with i led(fs) programmed to 20ma. the led current can be approximated by the following equation: i led = i led(fs) ?10 3 ? dac ? 63 63 ? ? ? ? ? ? where dac is the decimal value programmed into the i 2 c led dac register. for example with i led(fs) = 20ma and dac[5:0] = 101010 (42 decimal) i led equates to 2ma. table 10. i 2 c led dac register led dac register address: 00010010 sub-address: 00000010 bit name function b0 dac[0] 6-bit log dac code b1 dac[1] b2 dac[2] b3 dac[3] b4 dac[4] b5 dac[5] b6 n/a not usedno effect on operation b7 n/a not usedno effect on operation
ltc3577/ltc3577-1 42 3577fa operation table 11 shows the ? nal byte of data that can be written to at sub-address 0x03. this byte of data is referred to as the led pwm register. see the led pwm vs constant current operation section for detailed information on how to set the values of this register. table 11. led pwm register led pwm register address: 00010010 sub-address: 00000011 bit name function b0 pwmden[0] pwm denominator b1 pwmden[1] b2 pwmden[2] b3 pwmden[3] b4 pwmnum[0] pwm numerator b5 pwmnum[1] b6 pwmnum[2] b7 pwmnum[3] i 2 c output data one status byte may be read from the ltc3577. table 12 represents the status byte information. a 1 read back in the any of the bit positions indicates that the condition is true. for example, 1 read back from bit a3 indicate that ldo1 is enabled and regulating correctly. a status read from the ltc3577 captures the status information when the ltc3577 acknowledges its read address. table 12. i 2 c read register status register address: 00010011 sub-address: none bit name function a0 charge charge status (1 = charging) a1 stat[0] stat[1:0]; 00 = no fault 01 = too cold/hot 10 = battery overtemp 11 = battery fault a2 stat[1] a3 pgldo[1] ldo1 power good a4 pgldo[2] ldo2 power good a5 pgbck[1] buck1 power good a6 pgbck[2] buck2 power good a7 pgbck[3] buck3 power good bit a7 shows the power good status of buck3. a 1 indicates that buck3 is enabled and is regulating correctly. a 0 indi- cates that either buck3 is not enabled, or that the buck3 is enabled, but is out of regulation by more than 8%. bit a6 shows the power good status of buck2. a 1 indicates that buck2 is enabled and is regulating correctly. a 0 indi- cates that either buck2 is not enabled, or that the buck2 is enabled, but is out of regulation by more than 8%. bit a5 shows the power good status of buck1. a 1 indicates that buck1 is enabled and is regulating correctly. a 0 indi- cates that either buck1 is not enabled, or that the buck1 is enabled, but is out of regulation by more than 8%. bit a4 shows the power good status of ldo2. a 1 indicates that ldo2 is enabled and is regulating correctly. a 0 indi- cates that either ldo2 is not enabled, or that the ldo2 is enabled, but is out of regulation by more than 8%. bit a3 shows the power good status of ldo1. a 1 indicates that ldo1 is enabled and is regulating correctly. a 0 indi- cates that either ldo1 is not enabled, or that the ldo1 is enabled, but is out of regulation by more than 8%. bits a2 and a1 indicate the fault status of the charger circuit and are decoded in table 12. the too cold/hot state indicates that the thermistor temperature is out of the valid charging range (either below 0c or above 40c for a curve 1 thermistor) and that charging has paused until a return to valid temperature. the battery overtemp state indicates that the batterys thermistor has reached a critical temperature (above 50c for a curve 1 thermis- tor) and that long-term battery capacity may be seriously compromised if the condition persists. the battery fault state indicates that an attempt was made to charge a low battery (typically < 2.85v) but that the low voltage condition persisted for more than 1/2 hour. in this case charging has terminated. bit a0 indicates the status of the battery charger. a 1 in- dicates that the charger is enabled and is in the constant current charge state. in this case the battery is being charged unless the ntc thermistor is outside its valid charge range in which case charging is temporarily sus- pended but not complete. charging will continue once the
ltc3577/ltc3577-1 43 3577fa operation battery has returned to a valid charging temperature. a 0 in bit a0 indicates that charging has entered the end-of- charge state (h c/10 ) and is near v float or that charging has been terminated. charging can be terminated by reaching the end of the charge timer or by a battery fault as described previously. i 2 c write register map (see the i 2 c input data section for more details, all registers default to 0 when reset) ldo and buck contol register address: 00010010 sub-address: 00000000 bit name function b0 ldo1en enable ldo 1 b1 ldo2en enable ldo 2 b2 bk1brst buck1 burst mode enable b3 bk2brst buck2 burst mode enable b4 bk3brst buck2 burst mode enable b5 slewctl1 buck sw slew rate: 00 = 1ns, 01 = 2ns, 10 = 4ns, 11 = 8ns b6 slewctl2 b7 n/a not usedno effect on operation led control register address: 00010010 sub-address: 00000001 bit name function b0 en enable: 1= enable 0 = off b1 gr2 gradation gr[2:1]: 00 = 15ms, 01 = 460ms, 10 = 930ms, 11 = 1.85 seconds b2 gr1 b3 md1 mode md[2:1]: 00 = cc boost, 10 = pwm boost, 01 = hv boost b4 md2 b5 pwmc1 pwm clk pwmc[2:1]: 00 = 8.77khz, 01 = 4.39khz, 10 = 2.92khz, 11 = 2.19khz b6 pwmc2 b7 slewled led sw slew rate: 0/1 = fast/slow led dac register address: 00010010 sub-address: 00000010 bit name function b0 dac[0] 6-bit log dac code b1 dac[1] b2 dac[2] b3 dac[3] b4 dac[4] b5 dac[5] b6 n/a not usedno effect on 0peration b7 n/a not usedno effect on 0peration led pwm register address: 00010010 sub-address: 00000011 bit name function b0 pwmden[0] pwm denominator b1 pwmden[1] b2 pwmden[2] b3 pwmden[3] b4 pwmnum[0] pwm numerator b5 pwmnum[1] b6 pwmnum[2] b7 pwmnum[3] pushbutton interface operation state diagram/operation figure 18 shows the ltc3577 pushbutton state diagram. upon ? rst application of power (v bus , wall or bat) an internal power-on reset (por) signal places the pushbutton circuitry into the power-down (pdn1) state. one second after entering the pdn1 state the pushbutton circuitry will transition into the hard reset (hr) state. the following events cause the state machine to transition out of hr into the power-up (pup1) state: 1) on input low for 400ms (pb400ms) 2) application of external power (extpwr) 3) pwr_on input going high (pwr_on) pdn2 hrst pwr_on +uvlo hrst hrst 1sec 1sec por pdn1 pon poff pup1 hr 5sec pb400ms + extpwr + pwr_on pb400ms + extpwr + pwr_on pup2 5sec figure 18. pushbutton state diagram
ltc3577/ltc3577-1 44 3577fa operation upon entering the pup1 state, the pushbutton circuitry will sequence up the three step-down switching regula- tors in numerical order. ldo1, ldo2 and led backlight are enabled via i 2 c and do not take part in the power-up sequence of the pushbutton. five seconds after entering the pup1 state, the pushbutton circuitry will transition into the power-on (pon) state. note that the pwr_on input must be brought high before entering the pon state if the part is to remain in the pon state. pwr_on going low, or v out dropping to its undervoltage lockout (v out uvlo) threshold will cause the state machine to leave the pon state and enter the power-down (pdn2) state. the pdn1 and pdn2 states reset the i 2 c registers effectively shutting down the ldos and led backlight as well as disable all switching regulators together. the one second delay before leaving either power-down state allows all ltc3577 generated supplies to power down completely before they can be re-enabled. the same three events used to exit hr are also used to exit the poff state and enter pup2 state. the pup2 state operates in the same manner as the pup1 state previously described. the hard reset (hrst) event is generated by pressing and holding the pushbutton ( on input low) for 5 seconds. for a valid hrst event to occur the initial pushbutton applica- tion must start in the pup1, pup2 or pon state, but can end in any state. if a valid hrst event is present in pon, pdn2 or poff, then the state machine will transition to the pdn1 state and subsequently transition to the hr state one second later. in the hr state all supplies are disabled and the power- path circuitry is placed in an ultralow quiescent state to minimize battery drain. if no external charging supply is present (wall or v bus ) then the ideal diode is shut down disconnecting v out from bat. the ultralow power consumption in the hr state makes it ideal for shipping or long term storage, minimizing battery drain. in the hr state the battery monitoring circuit wakes up the charger every 150ms to sample the ntc thermistor for overtem- perature battery condition. to sample the ntc thermistor, the ideal diode is turned on charging v out up to v bat . as a consequence, any system load on v out will show up as a load on v bat . figure 26 shows an optional circuit to disconnect the system load from v out . power-up via pushbutton timing the timing diagram, figure 19, shows the ltc3577 power- ing up through application of the external pushbutton. for this example the pushbutton circuitry starts in the poff or hr state with a battery connected and all buck disabled. pushbutton application ( on low) for 400ms transitions the pushbutton circuitry into the pup state which brings wake hi-z for 5 seconds. wake going hi-z sequences buck1-3 up in numerical order. wake will stay hi-z if pwr_on is driven high before the 5 seconds pup period is over. if pwr_on is low or goes low after the 5 second period, wake will go low and buck1-3 will be shut down together. pg_dcdc is asserted once all enabled bucks are within 8% of their regulation voltage for 230ms. pbstat does not go low impedance with on going low during the power-up pushbutton application. pbstat will go low impedance with on on subsequent pushbutton applications once in the pup1, pup2 or pon states. the ldos and led backlight can be enabled and disabled at any time via i 2 c once in the pup1, pup2 or pon states. the pwr_on input can be driven via a p/c or by one of the buck outputs through a high impedance (100k typ) to keep the bucks enabled as described above. bat pbstat wake 400ms 230ms 1 2 3 bucks sequence up buck1-3 pg_dcdc pwr_on state poff/hr pup2/pup1 pon 3755 f19 v bus on (pb) 5sec figure 19. power-up via pushbutton timing
ltc3577/ltc3577-1 45 3577fa operation power-up via external power timing the timing diagram, figure 20, shows the ltc3577 power- ing up through application of the external power (v bus or wall). for this example the pushbutton circuitry starts in the poff or hr state with a battery connected and all buck disabled. 100ms after wall or v bus application the wake output goes hi-z for 5 seconds. the 100ms delay time allows the applied supply to settle. wake going hi-z sequences buck1-3 up in numerical order. wake will stay hi-z if the pwr_on input is driven high before the 5 seconds pup period is over. if pwr_on is low or goes low after the 5 second period, wake will go low and buck1-3 will be shut down together. pg_dcdc is asserted once all enabled bucks are within 8% of their regulation voltage for 230ms. the ldos and led backlight can be enabled and disabled via i 2 c any time after entering the pup1, pup2 or pon state. the pwr_on input can be driven via a p/c or one of the buck outputs through a high impedance (100k typ) to keep the bucks enabled as described above. without a battery present initial power application causes a power on reset which puts the pushbutton circuitry in the pdn2 state and subsequently the hr state 1 second later. in this case the pushbutton must be applied to enter the pup1 state after initial power application. power-up via pwr_on timing the timing diagram, figure 21, shows the ltc3577 powering up by driving pwr_on high. for this example the pushbutton circuitry starts in the poff or hr state with a battery connected and all bucks disabled. 50ms after pwr_on goes high the wake output goes hi-z for 5 seconds. wake going hi-z sequences buck1-3 up in numerical order. wake will stay hi-z as long as pwr_on is high at the end of the 5 second pup period. if pwr_on is low or goes low after the 5 second period, wake will go low and buck1-3 will be shut down together. pg_dcdc is asserted once all enabled bucks are within 8% of their regulation voltage for 230ms. the ldos and led backlight can be enabled and disabled via i 2 c any time after entering the pup1, pup2 or pon state. powering up via pwr_on is useful for applications containing an always on c. this allows the c to power the application up and down for house keeping and other activities outside the users control. bat pbstat wake 100ms 230ms 1 2 3 bucks sequence up buck1-3 pg_dcdc pwr_on state poff/hr pup2/pup1 pon 3755 f20 v bus on (pb) 5sec figure 20. power-up via external power timing pbstat pwr_on wake buck1-3 pg_dcdc state poff/hr pup2/pup1 pon bat on (pb) 230ms 3577 f21 1 2 3 bucks sequence up 5oms 5sec figure 21. power-up via pwr_on timing
ltc3577/ltc3577-1 46 3577fa operation power-down via pushbutton timing the timing diagram, figure 22, shows the ltc3577 powering down by c/p control. for this example the pushbutton circuitry starts in the pon state with a bat- tery connected and all bucks enabled. in this case the pushbutton is applied ( on low) for at least 50ms, which generates a low impedance on the pbstat output. after receiving the pbstat the c/p will drive the pwr_on input low. 50ms after pwr_on goes low the wake output will go low and the pushbutton circuitry will enter the pdn2 state. the bucks are disabled together at once upon entering the pdn2 state. once entering the pdn2 state a 1 second wait time is initiated before entering the poff state. during this 1 second time on and pwr_on inputs as well as external power application are ignored to allow all ltc3577 generated supplies to go low. though the above assumes a battery present, the same operation would take place with a valid external supply (v bus or wall) with or without a battery present. upon entering the pdn2 state the ldos and led backlight i 2 c registers are cleared effectively disabling both. if this is not desirable the ldos and led backlight should be disabled via i 2 c prior to entering the pdn2 state. holding on low through the 1 second power-down period will not cause a power-up event at end of the 1 second period. the on input must be brought high following the power-down event and then go low again to establish a valid power-up event. uvlo minimum off-time timing (low battery) the timing diagram, figure 23, assumes the battery is either missing or at a voltage below the v out uvlo threshold and the application is running via external power (v bus or wall). a glitch on the external supply causes v out to drop below the v out uvlo threshold temporarily. the v out uvlo condition will cause the pushbutton circuitry to transition from the pon state to the pdn2 state. upon entering the pdn2 state wake and pg_dcdc will go low while the bucks, ldos and led backlight power down together. if the external supply recovers after entering the pnd2 state such that v out is no longer in uvlo then the ltc3577 will transition back into the pup2 state once the pdn2 one second delay is complete. though not shown in figure 23, the pushbutton logic brie? y visits the poff state when transitioning between pdn2 and pup2. enter- ing the pup2 state will cause the bucks to sequence up as described previously in the power-up sections. the ldos and led backlight must be re-enabled via i 2 c once device is powered back up. pbstat pwr_on wake bucks pg_dcdc state pon pdn2 pup2 pon v bus/wall bat on (pb) 3577 f23 1sec bucks sequence up 1 2 3 230ms 5sec figure 23. uvlo minimum off-time figure 22. power-down via pushbutton timing pbstat pwr_on wake buck1-3 pg_dcdc state pon pdn2 poff v bus/wall bat on (pb) 3577 f22 1sec 50ms c/p control 50ms all bucks low
ltc3577/ltc3577-1 47 3577fa operation hard reset timing hard reset provides an ultralow power-down state for shipping or long-term storage as well as a way to power down the application in case of a software lock-up. in the case of software lock-up on is brought low by the user applying the pushbutton. if the user holds the pushbutton for 5 seconds a hard reset event (hrst) will occur placing the pushbutton circuitry in the pdn1 state. at this point the bucks, ldos and led backlight will all be shut down and wake and pg_dcdc will both go low. following a 1 second power-down period the pushbutton circuitry will enter the hard reset state (hr). holding on low through the 1 second power-down period will not cause a power-up event at end of the 1second period. the on must be brought high following the power-down event and then go low for again for 400ms to establish a valid power-up event as shown in figure 24. power-up sequencing figure 25 shows the actual power-up sequencing of the ltc3577. buck1, buck2 and buck3 are all initially disabled (0v). once the pushbutton has been applied ( on low) for 400ms, wake goes high and buck1 is enabled. buck1 slews up and enters regulation once enabled. the actual slew rate is controlled by the soft-start function of buck1 in conjunction with output capacitance and load (see the step-down switching regulator operation section for more information). when buck1 is within about 8% of ? nal regulation, buck2 is enabled and slews up into regulation. finally when buck2 is within about 8% of ? nal regulation, buck3 is enabled and slews up into regulation. 230ms after buck3 is within 8% of ? nal regulation the pg_dcdc output will go high impedance (not shown in figure 25). the regulators in figure 25 are slewing up with nominal output capacitors and no load. adding a load or increasing output capacitance on any of the outputs will reduce the slew rate and lengthen the time it takes the regulator to get into regulation. reducing the slew rate also pushes out the time until the next regulator is enabled proportionally. pbstat wake bucks pwr_on pg_dcdc state pon hr 1sec pdn1 pup bat on (pb) 3577 f24 1 2 3 400ms 5sec figure 24. hard reset timing 1 0 0v 0v 0v 50s/div 3577 f23 wake buck1 2v/div buck2 1v/div buck3 1v/div figure 25. power-up sequencing
ltc3577/ltc3577-1 48 3577fa operation layout and thermal considerations printed circuit board power dissipation in order to be able to deliver maximum charge current under all conditions, it is critical that the exposed ground pad on the backside of the ltc3577 package is soldered to a ground plane on the board. correctly soldered to 2500mm 2 ground plane on a double-sided 1oz. copper board the ltc3577 has a thermal resistance ( ja ) of ap- proximately 45c/w. failure to make good thermal contact between the exposed pad on the backside of the package and a adequately sized ground plane will result in thermal resistances far greater than 45c/w. the conditions that cause the ltc3577 to reduce charge current due to the thermal protection feedback can be approximated by considering the power dissipated in the part. for high charge currents with a wall adapter applied to v out , the ltc3577 power dissipation is approximately: p d = (v out C bat) ? i bat + p dregs where, p d is the total power dissipated, v out is the sys- tem supply voltage, bat is the battery voltage, and i bat is the battery charge current. p dregs is the sum of power dissipated on-chip by the step-down switching, ldo and led boost regulators. the power dissipated by a step-down switching regulator can be estimated as follows: p d(swx ) = boutx ? i out () ? 100 ? eff 100 where boutx is the programmed output voltage, i out is the load current and eff is the % ef? ciency which can be measured or looked up on an ef? ciency table for the programmed output voltage. the power dissipated on chip by a ldo regulator can be estimated as follows: p dldox = (v inldox C loutx) ? i out where loutx is the programmed output voltage, v inldox is the ldo supply voltage and i out is the ldo output load current. note that if the ldo supply is connected to one of the buck output, then its supply current must be added to the buck regulator load current for calculating the buck power loss. the power dissipated by the led boost regulator can be estimated as follows: p dled = i led ? 0.3v + r nswon ?i led ? boost v out ?1 ? ? ? ? ? ? 2 where boost is the output voltage driving the top of the led string, r nswon is the on-resistance of the sw n-fet (typically 330m), i led is the led programmed current sink. thus the power dissipated by all regulators is: p dregs = p dsw1 + p dsw2 + p dsw3 + p dldo1 + p dldo2 + p dled it is not necessary to perform any worst-case power dis- sipation scenarios because the ltc3577 will automatically reduce the charge current to maintain the die temperature at approximately 110c. however, the approximate ambi- ent temperature at which the thermal feedback begins to protect the ic is: t a = 110c C p d ? ja example: consider the ltc3577 operating from a wall adapter with 5v (v out ) providing 1a (i bat ) to charge a li-ion battery at 3.3v (bat). also assume p dregs = 0.3w, so the total power dissipation is: p d = (5v C 3.3v) ? 1a + 0.3w = 2w the ambient temperature above which the ltc3577 will begin to reduce the 1a charge current, is approximately t a = 110c C 2w ? 45c/w = 20c
ltc3577/ltc3577-1 49 3577fa operation the ltc3557 can be used above 20c, but the charge current will be reduced below 1a. the charge current at a given ambient temperature can be approximated by: p d = 110 c?t a ja = v out ? bat () ?i bat + p d(regs) thus: i bat = (110 c ? t a ) ja ? p dregs v out ? bat consider the above example with an ambient temperature of 55c. the charge current will be reduced to approxi- mately: i bat = 110 c?55 c 45c/w ? 0.3w 5v ? 3.3v i bat = 1.22w ? 0.3w 1.7v = 542ma if an external buck switching regulator controlled by the ltc3577 v c pin is used instead of a 5v wall adapter we see a signi? cant reduction in power dissipated by the ltc3577. this is because the external buck switching regulator will drive the powerpath output (v out ) to about 3.6v with the battery at 3.3v. if you go through the example above and substitute 3.6v for v out we see that thermal regulation does not kick in until about 83c. thus, the external high voltage buck regulator not only allows higher charging currents, but lower power dissipation means a cooler running application. printed circuit board layout when laying out the printed circuit board, the following list should be followed to ensure proper operation of the ltc3577: 1. the exposed pad of the package (pin 45) should connect directly to a large ground plane to minimize thermal and electrical impedance. 2. the step-down switching regulator input supply pins (v in12 and v in3 ) and their respective decoupling ca- pacitors should be kept as short as possible. the gnd side of these capacitors should connect directly to the ground plane of the part. these capacitors provide the ac current to the internal power mosfets and their drivers. its important to minimizing inductance from these capacitors to the pins of the ltc3577. connect v in12 and v in3 to v out through a short low impedance trace. 3. the switching power traces connecting sw1, sw2, and sw3 to their respective inductors should be minimized to reduce radiated emi and parasitic coupling. due to the large voltage swing of the switching nodes, sensitive nodes such as the feedback nodes (fbx, ldox_fb and led_ov) should be kept far away or shielded from the switching nodes or poor performance could result. 4. connections between the step-down switching regu- lator inductors and their respective output capacitors should be kept as short as possible. the gnd side of the output capacitors should connect directly to the thermal ground plane of the part. 5. keep the buck feedback pin traces (fb1, fb2, and fb3) as short as possible. minimize any parasitic capacitance between the feedback traces and any switching node (i.e. sw1, sw2, sw3, and logic signals). if necessary shield the feedback nodes with a gnd trace. 6. connections between the ltc3577 powerpath pins (v bus and v out ) and their respective decoupling ca- pacitors should be kept as short as possible. the gnd side of these capacitors should connect directly to the ground plane of the part. 7. the boost converter switching power trace connect- ing sw to the inductor should be minimized to reduce radiated emi and parasitic coupling. due to the large voltage swing of the sw node, sensitive nodes such as the feedback nodes (fbx, ldox_fb and led_ov) should be kept far away or shielded from this switching node or poor performance could result.
ltc3577/ltc3577-1 50 3577fa typical applications wall si2306bds si2333ds 5v wall adapter acpr v c ovgate v inldo2 42 4 41 30 v out 39 10f 13 ovsense 8 v bus clprog prog ldo1 ldo1_fb ldo2 ldo2_fb 40 usb 43 36 dv cc 10 sda scl 11 499k 12 wake pbstat 17 16 pwr_on 14 i lim0 1 i lim1 2 24 29 27 28 on 15 10f 6.2k d3 r1 optional overvoltage/ reverse voltage protection ltc3577 gnd v in3 6 44 2.2f v in12 chrg 37 idgate 38 bat 32 sw 18,19,20 ntcbias 34 ntc 35 2.2f 1k 100k bat 20f 1f 50v v out1 3.3v 500ma 100k li-ion 10h zlls400 6-led backlight 100k ntc si2333ds v out system load si2333ds (opt) si2306bds optional system load disconnect si2333ds 499k led_ov 9 i led 22 6m 324k led_fs 3 pg_dcdc 21 sw1 33 fb1 26 v inldo1 23 4.7h 20k 2.1k 2k + 1.02m 10pf 10f v out2 1.8v 500ma 649k sw2 31 fb2 25 4.7h 806k 10pf 10f 1f 1f v out3 1.2v 800ma 464k 470k 464k pushbutton sw3 5 fb3 7 45 3.3h 232k 10pf 232k 1.00m v ldo2 2.5v 150ma v ldo1 1.2v 75ma 10f 3577 ta02 499k dv cc sda scl wake pbstat pwr_on i lim0 i lim1 c/p rst 22nf figure 26. usb plus 5v adapter input charger, multichannel power supply and powerpath controller
ltc3577/ltc3577-1 51 3577fa typical applications figure 27. usb plus hv input charger, multichannel power supply and powerpath controller 1 6 nc wall si2306bds acpr ovgate v inldo2 42 9 8 7 11 441 30 v out 39 10f 13 ovsense 8 v bus clprog prog ldo1 ldo1_fb ldo2 ldo2_fb 40 usb 43 36 dv cc 10 sda scl 11 499k 12 wake pbstat 17 16 pwr_on 14 i lim0 1 i lim1 2 24 29 27 28 on 15 10f 6.2k optional overvoltage protection ltc3577 gnd v in3 6 44 2.2f v in12 chrg 37 idgate 38 bat 32 sw 18,19,20 ntcbias 34 ntc 35 2.2f 1k 100k bat 20f 1f 50v v out1 3.3v 500ma 100k li-ion 10h zlls400 10-led backlight 100k ntc si2333ds v out system load si2333ds (opt) dfls240l 6.8h 499k 22f 0.47f 100k optional high voltage buck input 150k 68nf 40.2k led_ov 9 i led 22 10m 324k led_fs 3 pg_dcdc 21 sw1 33 fb1 26 v inldo1 23 4.7h 20k 2.1k 2k + 1.02m 10pf 10f v out2 1.8v 500ma 649k sw2 31 fb2 25 4.7h 806k 10pf 10f 1f 1f v out3 1.2v 800ma 464k 470k 464k pushbutton sw3 5 fb3 7 45 3.3h 232k 10pf 232k 1.00m v ldo2 2.5v 150ma v ldo1 1.2v 75ma 10f 3577 ta03 499k dv cc sda scl wake pbstat pwr_on i lim0 i lim1 c/p rst v c v c gnd pg nc fb sync 10 rt 5 4 run/ss v in bd 3 sw 2 boost lt3480 4.7f hv in 8v to 38v (transients to 60v) 22nf
ltc3577/ltc3577-1 52 3577fa 4.00 p 0.10 5.60 ref 6.10 0.05 2.56 0.05 2.64 0.05 1.70 0.05 7.50 0.05 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 43 1 2 44 bottom viewexposed pad 2.40 ref 3.10 0.05 4.50 0.05 7.00 p 0.10 5.60 ref 0.75 p 0.05 0.20 p 0.05 (uff44ma) qfn ref ? 1107 0.40 bsc 0.98 0.10 0.200 ref 0.00 C 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 2.40 ref 2.64 0.10 0.40 p 0.10 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 s 45 o chamfer 2.56 0.10 1.70 0.10 2.76 0.10 0.74 0.10 r = 0.10 typ r = 0.10 typ r = 0.10 typ 0.74 0.10 0.40 bsc package outline 0.20 0.05 2.02 0.05 2.76 0.05 0.98 0.05 1.48 0.05 0.70 0.05 package description uff package variation: uffma 44-lead plastic qfn (4mm 7mm) (reference ltc dwg # 05-08-1762 rev ?)
ltc3577/ltc3577-1 53 3577fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a nov 09 changes to features change to absolute maximum ratings add note 16 text changes to pin functions changes to operation section changes to typical application circuits 1 3 10 18 44 50, 51
ltc3577/ltc3577-1 54 3577fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 1209 rev a ? printed in usa related parts part number description comments ltc3455 dual dc/dc converter with usb power manager and li-ion battery charger seamless transition between input power sources: li-ion battery, usb and 5v wall adapter. two high ef?ciency dc/dc converters: up to 96%. full featured li-ion battery charger with accurate usb current limiting (500ma/100ma). pin selectable burst mode operation. hot swap? output for sdio and memory cards. 24-lead 4mm 4mm qfn package ltc3456 2-cell, multi-output dc/dc converter with usb power manager seamless transition between 2-cell battery, usb and ac wall adapter input power sources. main output: fixed 3.3v output, core output: adjustable from 0.8v to v batt(min) . hot swap output for memory cards. power supply sequencing: main and hot swap accurate usb current limiting. high frequency operation: 1mhz. high ef?ciency: up to 92%. 24-lead 4mm 4mm qfn package ltc3552 standalone linear li-ion battery charger with adjustable output dual synchronous buck converter synchronous buck converter, ef?ciency: >90%, adjustable outputs at 800ma and 400ma, charge current programmable up to 950ma, usb compatible, 16-lead 5mm 3mm dfn package ltc3555 i 2 c controlled high ef? ciency usb power manager plus triple step-down dc/dc maximizes available power from usb port, bat-track, instant-on operation, 1.5a max charge current, 180m ideal diode with <50m option, 3.3v/25ma always-on ldo, three synchronous buck regulators, one 1a buck-boost regulator, 4mm 5mm qfn28 package ltc3556 high ef? ciency usb power manager plus dual buck plus buck-boost dc/dc maximizes available power from usb port, bat-track, instant-on operation, 1.5a max charge current, 180m ideal diode with <50m option, 3.3v/25ma always-on ldo, two 400ma synchronous buck regulators, one 1a buck-boost regulator, 4mm 5mm qfn28 package ltc3557/ ltc3557-1 usb power manager with li- ion/polymer charger and triple synchronous buck converter complete multifunction assp: linear power manager and three buck regulators charge current programmable up to 1.5a from wall adapter input, thermal regulation synchronous buck ef?ciency: >95%, adj outputs: 0.8v to 3.6v at 400ma/400ma/600ma bat-track adaptive output control, 200m ideal diode, 4mm 4mm qfn28 package, -1 version has 4.1v float voltage. ltc3566 ltc3567 switching usb power manager with li-ion/polymer charger, 1a buck-boost converter plus ldo multifunction pmic: switchmode power manager and 1a buck-boost regulator + ldo, charge current programmable up to 1.5a from wall adapter input, thermal regulation synchronous buck-boost converters ef? ciency: >95%, adj output: down to 0.8v at 1a, bat-track adaptive output control, 180m ideal diode, ltc3567 has i 2 c interface, 4mm 4mm qfn24 package ltc3576/-1 switching usb power manager with usb otg + triple step-down dc/dcs complete multi-function pmic: bi-directional switching power manager + 3 bucks + ldo, adj output down to 0.8v at 400ma/400ma/1a, overvoltage protection, usb on-the-go, charge current programmable up to 1.5a from wall adapter input, thermal regulation, i 2 c, hi-voltage bat-track buck interface, 180m ideal diode, 4mm 6mm qfn-38 package ltc3586 switching usb power manager with li-ion/polymer charger plus dual buck plus buck-boost plus boost dc/dc maximizes available power from usb port, bat-track, instant-on operation, 1.5a max charge current, 180m ideal diode with <50m option, 3.3v/25ma always-on ldo, two 400ma synchronous buck regulators, one 1a buck-boost regulator, one 600ma boost regulator, 4mm 6mm 38-pin qfn package ltc4085/ ltc4085-1 usb power manager with ideal diode controller and li-ion charger charges single cell li-ion batteries directly from a usb port, thermal regulation, 200m ideal diode with <50m option, 4mm 3mm dfn14 package, -1 version has 4.1v float voltage. ltc4088 high ef?ciency usb power manager and battery charger maximizes available power from usb port, bat-track, instant-on operation, 1.5a max charge current, 180m ideal diode with <50m option, 3.3v/25ma always-on ldo, 4mm 3mm dfn14 package ltc4088-1 high ef? ciency usb power manager and battery charger with regulated output voltage maximizes available power from usb port, bat-track, instant-on operation, 1.5a max charge current, 180m ideal diode with <50m option, automatic charge current reduction maintains 3.6v minimum v out , battery charger disabled when all logic inputs are grounded, 3mm 4mm dfn14 package ltc4088-2 high ef? ciency usb power manager and battery charger with regulated output voltage maximizes available power from usb port, bat-track, instant-on operation, 1.5a max charge current, 180m ideal diode with <50m option, automatic charge current reduction maintains 3.6v minimum v out , 3mm 4mm dfn14 package ltc4098 usb-compatible switchmode power manager with ovp high v in : 38v operating, 60v transient; 66v ovp . maximizes available power from usb port, bat-track, instant-on operation, 1.5a max charge current from wall, 600ma charge current from usb, 180m ideal diode with <50m option; 3mm 4mm ultrathin qfn20 package hot swap is a trademark of linear technology corporation.

▲Up To Search▲

Price & Availability of LTC3577EUFF-1TRPBF

	To Download LTC3577EUFF-1TRPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .